参数资料
型号: DS1986-F3
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: Programmable ROM
英文描述: 64K X 1 OTPROM, MEDB2
封装: MICROCAN-2
文件页数: 14/28页
文件大小: 680K
代理商: DS1986-F3
DS1986
21 of 28
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 10. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS1986 to the master
by triggering a delay circuit in the DS1986. During write time slots, the delay circuit determines when the
DS1986 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS1986 will hold the data line low overriding the 1 generated by the master. If
the data bit is a “1”, the iButton will leave the read data time slot unchanged.
PROGRAM PULSE
To copy data from the 8-bit scratchpad to the EPROM Data or Status Memory, a program pulse of 12
volts is applied to the data line after the bus master has confirmed that the CRC for the current byte is
correct. During programming, the bus master controls the transition from a state where the data line is
idling high via the pull-up resistor to a state where the data line is actively driven to a programming
voltage of 12 volts providing a minimum of 10 mA of current to the DS1986. This programming voltage
(Figure 11) should be applied for 480
μs, after which the bus master returns the data line to an idle high
state controlled by the pull-up resistor. Note that due to the high voltage programming requirements for
any 1-Wire EPROM device, it is not possible to multi-drop non-EPROM based 1-Wire devices with the
DS1986 during programming. An internal diode within the non-EPROM based 1-Wire devices will
attempt to clamp the data line at approximately 8 volts and could potentially damage these devices.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9
Regular Speed
Overdrive Speed
480
μs ≤ tRSTL < ∞
48
μs ≤ tRSTL < 80 μs
480
μs ≤ tRSTH < ∞ (includes recovery time) 48 μs ≤ tRSTH < ∞
15
μs ≤ tPDH < 60 μs
2
μs ≤ tPDH < 6 μs
60
μs ≤ tPDL < 240 μs
8
μs ≤ tPDL < 24 μs
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960
μs.
RESISTOR
MASTER
DS1986
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PDF描述
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