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参数资料
| 型号： | DS1996L-F5+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 5/19页 |
| 文件大小： | 0K |
| 描述： | IBUTTON MEMORY 64KBit F5 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| RoHS指令信息： | IButton RoHS Compliance Plan |
| 标准包装： | 15 |
| 系列： | iButton® |
| 存储容量： | 8KB |
| 存储器类型： | NVRAM |
| 产品目录页面： | 1431 (CN2011-ZH PDF) |
DS1996
MEMORY
The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages
called memory. The DS1996 contains 256 pages which comprise the 65536-bit SRAM. The scratchpad is
an additional page that acts as a buffer when writing to memory.
ADDRESS REGISTERS AND TRANSFER STATUS
Because of the serial data transfer, the DS1996 employs three address registers, called TA1, TA2 and E/S
(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be
written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte
counter and Transfer Status register. It is used to verify data integrity with Write commands. Therefore,
the master only has read access to this register. The lower 5 bits of the E/S register indicate the address of
the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S
register, called PF or ”partial byte flag,” is set if the number of data bits sent by the master is not an
integer multiple of 8. Bit 6, OF or ”Overflow,” is set if more bits are sent by the master than can be stored
in the scratchpad. Note that the lowest 5 bits of the target address also determine the address within the
scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the target
address for a Write command is 13CH for example, then the scratchpad will store incoming data
beginning at the byte offset 1CH and will be full after only 4 bytes. The corresponding ending offset in
this example is 1FH. For best economy of speed and efficiency, the target address for writing should
point to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 32-byte capacity of the
scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write one or
several contiguous bytes somewhere within a page. The ending offset together with the Partial and
Overflow Flag is mainly a means to support the master checking the data integrity after a Write
command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag
to indicate that the data stored in the scratchpad has already been copied to the target memory address.
Writing data to the scratchpad clears this flag.
WRITING WITH VERIFICATION
To write data to the DS1996, the scratchpad has to be used as intermediate storage. First the master issues
the Write Scratchpad command to specify the desired target address, followed by the data to be written to
the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad
and to verify data integrity. As preamble to the scratchpad data, the DS1996 sends the requested target
address TA1 and TA2 and the contents of the E/S register. If one of the flags OF or PF is set, data did not
arrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to
write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not
recognized by the iButton. If everything went correctly, all three flags are cleared and the ending offset
indicates the address of the last byte written to the scratchpad. Now the master can continue verifying
every data bit. After the master has verified the data, it has to send the Copy Scratchpad command. This
command must be followed exactly by the data of the three address registers TA1, TA2 and E/S as the
master has read them verifying the scratchpad. As soon as the iButton has received these bytes, it will
copy the data to the requested location beginning at the target address.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the
memory. An example follows the flowchart. The communication between master and DS1996 takes place
either at regular speed (default, OD= 0) or at Overdrive Speed (OD= 1). If not explicitly set into the
Overdrive Mode the DS1996 assumes regular speed.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1996L-F5/A18 | 功能描述:iButton RoHS:否 存储类型:SRAM 存储容量:512 B 组织: 工作电源电压:3 V to 5.25 V 接口类型:1-Wire 最大工作温度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封装 / 箱体:F5 MicroCan 制造商:Maxim Integrated |
| DS1996L-F5+ | 功能描述:iButton 64Kb Memory iButton RoHS:否 存储类型:SRAM 存储容量:512 B 组织: 工作电源电压:3 V to 5.25 V 接口类型:1-Wire 最大工作温度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封装 / 箱体:F5 MicroCan 制造商:Maxim Integrated |
| DS-19P | 制造商:Pan Pacific 功能描述: |
| DS-19S | 制造商:Pan Pacific 功能描述: |
| DS1-A | 制造商:Sliger Designs, Inc. 功能描述:CPC CASE W/ POWER SUPPLY (SPI220LE) FANS, SWITCH ECT. - Bulk |
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