参数资料
型号: DS21348GN
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, BGA49
封装: CABGA-49
文件页数: 13/44页
文件大小: 1078K
代理商: DS21348GN
MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-IQ, PMICs with Dynamic
Voltage Management for Mobile Applications
20
Pin Description (continued)
PIN
MAX8660 MAX8661
NAME
FUNCTION
16
PG2
REG2 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV
kit data sheet for more information.
17
IN8
REG8 Input Power Connection. IN8 must be connected to IN.
18
IN
Main Battery Input. This input provides power to the IC. Connect a 0.47F ceramic capacitor from
IN to AGND.
19
AGND
Analog Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit
data sheet for more information.
20
V8
REG8 Always-On 3.3V LDO Output. REG8 is the first regulator that powers up in the
MAX8660/MAX8661. REG8 is supplied from IN and supplies up to 30mA. V8 is internally pulled to
AGND through 1.5k
during IN undervoltage or overvoltage lockout. Connect V8 to VCC_BBATT
on Marvell PXA3xx processors.
21
LBF
Low-Battery Detect Falling Input. The LBF threshold is 1.20V. Connect LBF to LBR for 50mV
hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBF sets the falling voltage at
which
LBO goes low. See the Low-Battery Detector (
LBO, LBF, LBR) section for more information.
22
LBR
Low-Battery Detect Rising Input. The LBR threshold is 1.25V. Connect LBF to LBR for 50mV
hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBR sets the rising voltage at
which
LBO goes high. See the Low-Battery Detector (
LBO, LBF, LBR) section for more
information.
23
MR
Manual Reset Input. A low
MR input causes RSO to go low and resets all serial programmed
registers to their default values. See the Reset Output (
RSO) and MR Input section for more
information.
24
RAMP
Ramp-Rate Input. Connect a resistor from RAMP to AGND to set the regulator ramp rates. See the
Ramp-Rate Control (RAMP) section for more information.
25
EN5
REG5 Enable Input. Drive EN5 high to turn on REG5. EN5 has hysteresis so an RC can be used to
implement manual sequencing with respect to other inputs. EN5 is typically driven by the SYS_EN
output of an Marvell PXA3xx processor.
26
PG3
REG3 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV
kit data sheet for more information.
27
LX3
REG3 Switching Node. Connect LX3 to the REG3 inductor. LX3 is high impedance when REG3 is
shut down.
28
PV3
REG3 Power Input. Connect a 4.7
F ceramic capacitor from PV3 to PG3. All PV pins and IN must
be connected together externally.
29
RSO
Open-Drain Reset Output.
RSO typically connects to the nRESET input on an applications
processor. An output low from the MAX8660/MAX8661
RSO resets all serial programmed
registers to their default values and causes the processor to enter its reset state. See the Reset
Output (
RSO) and MR Input section for more information.
30
V3
REG3 Voltage Sense Input. Connect V3 directly to the REG3 output voltage. The output voltage is
adjustable from 0.725V to 1.8V through the serial interface. V3 is internally pulled to AGND through
550
when REG3 is shut down. V3 connects to VCC_APPS on Marvell PXA3xx processors.
31
EN34
REG3 and REG4 Active-High Hardware Enable Input. Drive EN34 high to enable both REG3 and
REG4. Drive EN34 low to allow the serial interface to enable REG3 and REG4 independently.
EN34 has hysteresis so an RC can be used to implement manual sequencing with respect to
other inputs. EN34 is typically driven by the PWR_EN output of an Marvell PXA3xx processor. See
the REG3/REG4 Enable (EN34, EN3, EN4) section for more information.
相关PDF资料
PDF描述
DS21348T DATACOM, PCM TRANSCEIVER, PQFP44
DS21348TN DATACOM, PCM TRANSCEIVER, PQFP44
DS21348G DATACOM, PCM TRANSCEIVER, BGA49
DS21Q348N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q348 DATACOM, PCM TRANSCEIVER, PBGA144
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