参数资料
型号: DS21354DK
厂商: Maxim Integrated Products
文件页数: 6/21页
文件大小: 0K
描述: KIT DESIGN FOR DS21354
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电信,调帧器和线路接口装置(LIU)
已用 IC / 零件: DS21354
已供物品: 板,子卡,CD
DS21354DK
revision
Control Registers
The control registers are used primarily to control several banks of FET switches that route clocks and backplane
signals. Please note that certain register settings cause line contention, e.g., setting SWITCH1.4 and SWITCH2.4
both to 0 would drive MCLK with both 1.544MHz and 2.048MHz.
SWITCH1: PIN TO 1.544MHz (OFFSET = 0x0011) INITIAL VALUE = 0xF
(MSB)
(LSB)
MCLK
TCLK
RSYSCLK
TSYSCLK
NAME
MCLK
TCLK
RSYSCLK
TSYSCLK
POSITION
SWITCH1.3
SWITCH1.2
SWITCH1.1
SWITCH1.0
FUNCTION
0 = Connect MCLK to the 1.544MHz clock
1 = Open Switch 1.4
0 = Connect TCLK to the 1.544MHz clock
1 = Open Switch 1.3
0 = Connect RSYSCLK to the 1.544MHz clock
1 = Open Switch 1.2
0 = Connect TSYSCLK to the 1.544MHz clock
1 = Open Switch 1.1
SWITCH2: PIN TO 2.048MHz (Offset = 0X0012) INITIAL VALUE = 0x3
(MSB)
(LSB)
MCLK
TCLK
RSYSCLK
TSYSCLK
NAME
MCLK
TCLK
RSYSCLK
TSYSCLK
POSITION
SWITCH2.3
SWITCH2.2
SWITCH2.1
SWITCH2.0
FUNCTION
0 = Connect MCLK to the 2.048MHz clock
1 = Open Switch 2.4
0 = Connect TCLK to the 2.048MHz clock
1 = Open Switch 2.3
0 = Connect RSYSCLK to the 2.048MHz clock
1 = Open Switch 2.2
0 = Connect TSYSCLK to the 2.048MHz clock
1 = Open Switch 2.1
SWITCH3: PIN-TO-PIN CONNECT (Offset = 0X0013) INITIAL VALUE = 0xF
(MSB)
(LSB)
TSS_RS
TCL_RC
RSY_RC
TSY_RC
NAME
TSS_RS
TCL_RC
RSY_RC
TSY_RC
POSITION
SWITCH3.3
SWITCH3.2
SWITCH3.1
SWITCH3.0
FUNCTION
0 = Connect TSSYNC to RSYNC
1 = Open Switch 3.4
0 = Connect TCLK to RCLK
1 = Open Switch 3.3
0 = Connect RSYSCLK to RCLK
1 = Open Switch 3.2
0 = Connect TSYSCLK to RCLK
1 = Open Switch 3.1
6 of 21
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