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参数资料
| 型号： | DS2141AQ/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 23/39页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER T1 5V 44-PLCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 500 |
| 控制器类型： | T1 控制器 |
| 接口： | 并行/串行 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 10mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
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DS2141A
3 of 39
DS2141A FEATURES
Parallel control port
Large error counters
Onboard dual 2-frame elastic store
FDL support circuitry
Robbed-bit signaling extraction and insertion
Programmable output clocks
Fully independent transmit and receive sections
Frame sync generation
Error-tolerant yellow and blue alarm detection
Output pin test mode
Payload loopback capability
SLC-96 support
Remote loop up/down code detection
Loss of transmit clock detection
Loss of receive clock detection
1's density violation detection
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1TCLK
I
Transmit Clock. 1.544 MHz primary clock.
2TSER
I
Transmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
3TCHCLK
O
Transmit Channel Clock. 192 kHz clock which pulses high during
the LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
4
5
TPOS
TNEG
O
Transmit Bipolar Data. Updated on rising edge of TCLK.
6-13
AD0-AD7
I/O
Address/Data Bus. An 8-bit multiplexed address/data bus.
14
BTS
I
Bus Type Select. Strap high to select Motorola bus timing; strap
low to select Intel bus timing. This pin controls the function of
RD
(DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
15
RD
(DS)
I
Read Input (Data Strobe).
16
CS
I
Chip Select. Must be low to read or write the port.
17
ALE(AS)
I
Address Latch Enable (Address Strobe). A positive-going edge
serves to demultiplex the bus.
18
WR
(R/ W )
I
Write Input (Read/Write).
19
RLINK
O
Receive Link Data. Updated with either FDL data (ESF) or Fs-bits
(D4) or Z-bits (ZBTSI) one RCLK before the start of a frame. See
Section 13 for timing details.
20
VSS
-
Signal Ground. 0.0 volts.
21
RLCLK
O
Receive Link Clock. 192 kHz clock which pulses high during the
LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
22
RCLK
I
Receive Clock. 1.544 MHz primary clock.
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| DS2143Q | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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