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参数资料
| 型号： | DS2141AQ+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/39页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER T1 5V 44-PLCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 500 |
| 控制器类型： | T1 控制器 |
| 接口： | 并行/串行 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 10mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
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DS2141A
21 of 39
RFDL: RECEIVE FDL REGISTER (28h)
(MSB)
(LSB)
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RFDL7
RFDL.7
MSB of the Received FDL Code.
RFDL0
RFDL.0
LSB of the Received FDL Code.
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs-
bits. The LSB is received first.
RFDLM1: RECEIVE FDL MATCH REGISTER 1 (29h)
RFDLM2: RECEIVE FDL MATCH REGISTER 2 (2Ah)
(MSB)
(LSB)
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RFDL7
RFDL.7
MSB of the FDL Match Code.
RFDL0
RFDL.0
LSB of the FDL Match Code.
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RFDLM1/RFDLM2), RSR2.2 will be set to a 1 and the INT2 will go active if enabled via IMR2.2.
6.2 Transmit Section
The transmit section will shift out either the FDL (in the ESF framing mode) or the Fs-bits (in the D4
framing mode) contained in the Transmit FDL register (TFDL) into the T1 data stream. When a new
value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the
outgoing T1 data stream. After the full 8 bits have been shifted out, the DS2141A will signal the host
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The
INT2 will also toggle low if enabled via IMR2.3. The user has 2 ms (1.5 ms in SLC-96 applications) to
update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be
transmitted once again.
The DS2141A also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1's should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2141A will
automatically look for five 1's in a row. If it finds such a pattern, it will automatically insert a 0 after the
five 1's. The CCR2.0 bit should always be set to a 1 when the DS2141A is inserting the FDL. More on
how to use the DS2141A in FDL applications is covered in a separate Application Note.
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| DS2143Q | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2143Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC CONTROLLER E1 5V LP 44-PLCC 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs E1 Controller w/Elastic Store |
| DS2143Q/T&R | 功能描述:网络控制器与处理器 IC E1 Controller w/Elastic Store RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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