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参数资料
| 型号： | DS21448DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/60页 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN LIU DS21448 T1/J1/E1 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 电信，线路接口单元（LIU） |
| 已用 IC / 零件： | DS21448 |
| 已供物品： | 板，子卡，CD |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
26 of 60
RIR1 (08H): Receive Information Register 1
(MSB)
(LSB)
ZD
16ZD
HBD
RCLC
RUA1C
JALT
—
NAME
POSITION
FUNCTION
ZD
(Latched)
RIR1.7
Zero Detect. This bit is set when a string of at least four (ETS = 0) or eight (ETS = 1)
consecutive 0s (regardless of the length of the string) have been received. This bit is cleared
when read.
16ZD
(latched)
RIR1.6
16 Zero Detect. This is set when at least 16 consecutive 0s (regardless of the length of the
string) have been received. This bit is cleared when read.
HBD
(Latched)
RIR1.5
HDB3/B8ZS Word Detect. This is set when an HDB3 (ETS = 0) or B8ZS (ETS = 1) codeword
is detected independently of the receive HDB3/B8ZS mode (CCR4.6) being enabled. This bit
is cleared when read. It is useful for automatically setting the line coding.
RCLC
(Latched)
RIR1.4
RCL Clear. Set when the RCL alarm has met the clear criteria defined in Table 5-A. This bit
is cleared when read.
RUA1C
(Latched)
RIR1.3
Receive Unframed All-Ones Clear. This bit is set when the unframed all-ones signal is no
longer detected. This bit is cleared when read (Table 5-A).
JALT
(Latched)
RIR1.2
Jitter Attenuator Limit Trip. This bit is set when the jitter attenuator FIFO reaches within 4 bits
of its useful limit. This bit is cleared when read and is useful for debugging jitter attenuation
operation.
N/A
RIR1.1
Not Assigned. Could be any value when read.
N/A
RIR1.0
Not Assigned. Could be any value when read.
RIR2 (09H): Receive Information Register 2
(MSB)
(LSB)
RL3
RL2
RL1
RL0
—
ARLB
SEC
NAME
POSITION
FUNCTION
RL3
(Real Time)
RIR2.7
Receive Level Bit 3 (Table 5-B)
RL2
(Real Time)
RIR2.6
Receive Level Bit 2
RL1
(Real Time)
RIR2.5
Receive Level Bit 1 (Table 5-B)
RL0
(Real Time)
RIR2.4
Receive Level Bit 0
N/A
RIR2.3
Not Assigned. Could be any value when read.
N/A
RIR2.2
Not Assigned. Could be any value when read.
ARLB
(Real Time)
RIR2.1
Automatic Remote Loopback Detected. This bit is set to 1 when the automatic remote
loopback circuitry has detected the presence of a loop-up code for 5 seconds. It remains set
until the automatic RLB circuitry has detected the loop-down code for 5 seconds. See
Section 11 for more details. This bit is forced low when the automatic RLB circuitry is
disabled (CCR6.5 = 0).
SEC
(Latched)
RIR2.0
One-Second Timer. This bit is set to 1 on one-second boundaries as timed by the device,
based on the RCLK. It is cleared when read.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21448G+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448GN+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448L | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448L+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21448L+W | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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