参数资料
型号: DS2151QB+
厂商: Maxim Integrated Products
文件页数: 2/60页
文件大小: 0K
描述: IC TXRX T1 1-CHIP 5V LP 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 26
功能: 单芯片收发器
接口: T1
电路数: 1
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 65mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 管件
包括: 警报检测器和发生器,CSU 回路代码发生器和检测器,DSX-1和CSU 线路补偿发生器
产品目录页面: 1429 (CN2011-ZH PDF)
DS2151Q
10 of 60
4 CONTROL REGISTERS
The operation of the DS2151Q is configured via a set of eight registers. Typically, the control registers
are only accessed when the system is first powered up. Once the DS2151Q has been initialized, the
control registers will only need to be accessed when there is a change in the system configuration. There
are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and
TCR2), a Line Interface Control Register (LICR), and three Common Control Registers (CCR1, CCR2,
and CCR3). Seven of the eight registers are described below. The LICR is described in Section 13.
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 2B Hex)
(MSB)
(LSB)
LCVCRF
ARC
OOF1
OOF2
SYNCC
SYNCT
SYNCE
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
LCVCRF
RCR1.7
Line Code Violation Count Register Function Select.
0 = do not count excessive 0s
1 = count excessive 0s
ARC
RCR1.6
Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
OOF1
RCR1.5
Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
OOF2
RCR1.4
Out Of Frame Select 2.
0 = follow RCR1.5
1 = 2/6 frame bits in error
SYNCC
RCR1.3
Sync Criteria.
In D4 Framing Mode
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
SYNCT
RCR1.2
Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
SYNCE
RCR1.1
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
RESYNC
RCR1.0
Resync. When toggled from low to high, a resynchronization
of the receive side framer is initiated. Must be cleared and set
again for a subsequent resync.
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