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参数资料
| 型号： | DS2153Q |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQCC44 |
| 封装： | 0.652 INCH, PLASTIC, LCC-44 |
| 文件页数： | 6/18页 |
| 文件大小： | 292K |
| 代理商： | DS2153Q |
MAX13442E/MAX13443E/MAX13444E
±15kV ESD-Protected, ±80V Fault-Protected,
Fail-Safe RS-485/J1708 Transceivers
14
______________________________________________________________________________________
VCC
TIMER
DE
(HOT SWAP)
15
μs
100
μA
M1
M2
5.6k
Ω
2mA
Figure 10. Simplified Structure of the Driver Enable Pin (DE)
Hot-Swap Capability
Hot-Swap Inputs
Inserting circuit boards into a hot, or powered, back-
plane may cause voltage transients on DE, RE, and
receiver inputs A and B that can lead to data errors. For
example, upon initial circuit board insertion, the proces-
sor undergoes a power-up sequence. During this period,
the high-impedance state of the output drivers makes
them unable to drive the MAX13442E/MAX13443E/
MAX13444E enable inputs to a defined logic level.
Meanwhile, leakage currents of up to 10A from the
high-impedance output, or capacitively coupled noise
from VCC or GND, could cause an input to drift to an
incorrect logic state. To prevent such a condition from
occurring, the MAX13442E/MAX13443E/MAX13444E
feature hot-swap input circuitry on DE, and RE to guard
against unwanted driver activation during hot-swap sit-
uations. The MAX13444E has hot-swap input circuitry
only on RE. When VCC rises, an internal pulldown (or
pullup for RE) circuit holds DE low for at least 10s, and
until the current into DE exceeds 200A. After the initial
power-up sequence, the pulldown circuit becomes
transparent, resetting the hot-swap tolerable input.
Hot-Swap Input Circuitry
At the driver-enable input (DE), there are two NMOS
devices, M1 and M2 (Figure 10). When VCC ramps from
zero, an internal 15s timer turns on M2 and sets the
SR latch, which also turns on M1. Transistors M2, a
2mA current sink, and M1, a 100A current sink, pull
DE to GND through a 5.6k
Ω resistor. M2 pulls DE to the
disabled state against an external parasitic capaci-
tance up to 100pF that may drive DE high. After 15s,
the timer deactivates M2 while M1 remains on, holding
DE low against three-state leakage currents that may
drive DE high. M1 remains on until an external current
source overcomes the required input current. At this
time, the SR latch resets M1 and turns off. When M1
turns off, DE reverts to a standard, high-impedance
CMOS input. Whenever VCC drops below 1V, the input
is reset.
A complementary circuit for RE uses two PMOS
devices to pull RE to VCC.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
Ω
RD
1.5k
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 9a. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
AMPERES
Figure 9b. Human Body Model Current Waveform
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2153Q-A5 | 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS2153Q-A5/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC |
| DS2153Q-A5/T&R | 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS2153Q-A7 | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2153Q-A7/T&R | 制造商:Maxim Integrated Products 功能描述:E1 SINGLE CHIP XCVR REV A7 T&R - Tape and Reel |
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