参数资料
型号: DS21552L
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封装: 14 X 14 MM, LQFP-100
文件页数: 3/139页
文件大小: 1208K
代理商: DS21552L
DS21352/DS21552
100 of 137
SELECT-IR-SCAN
All test registers retain their previous state. The instruction register will remain unchanged during this
state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will
initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the
controller back into the Test-Logic-Reset state.
CAPTURE-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the
controller will enter the Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will
enter the Shift-IR state.
SHIFT-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as
all test registers, remain at their previous states. A rising edge on JTCLK with JTMS HIGH will move
the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW will keep the controller in
the Shift-IR state while moving data one stage thorough the instruction shift register.
EXIT1-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH
on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning
process.
PAUSE-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK
will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is
LOW during a rising edge on JTCLK.
相关PDF资料
PDF描述
DS21552LN DATACOM, PCM TRANSCEIVER, PQFP100
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