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参数资料
型号： DS21554LN
厂商： Maxim Integrated Products
文件页数： 93/124页
文件大小： 0K
描述： IC TXRX E1 1-CHIP 5V 100-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
产品变化通告： Product Discontinuation 20/Feb/2012
标准包装： 90
功能： 单芯片收发器
接口： E1，HDLC，J1，T1
电路数： 1
电源电压： 4.75 V ~ 5.25 V
电流 - 电源： 75mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-LQFP（14x14）
包装： 托盘
包括： 远程和 AIS 警报检测器 / 发生器
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
70 of 124
14.
HDLC CONTROLLER FOR THE Sa BITS OR DS0
The DS21354/DS21554 can extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any
multiple of DS0 or sub-DS0 channels. The SCT contains a complete HDLC controller (see Section 14).
14.1.
General Overview
The DS21354/DS21554 contain a complete HDLC controller with 64-byte buffers in both the transmit
and receive directions The HDLC controller performs all the necessary overhead for generating and
receiving an HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns
to the HDLC data stream.
There are 11 registers that the host uses to operate and control the operation of the HDLC controller. A
brief description of the registers is shown in Table 14-1.
Table 14-1. HDLC Controller Register List
NAME
FUNCTION
HDLC Control Register (HCR)
HDLC Status Register (HSR)
HIMR Interrupt Mask Register (HIMR)
general control over the HDLC controller
key status information for both transmit and receive
directions allows/stops status bits to/from causing an
interrupt
Receive HDLC Information register (RHIR)
Receive HDLC FIFO Register (RHFR)
Receive HDLC DS0 Control Register 1 (RDC1)
Receive HDLC DS0 Control Register 2 (RDC2)
status information on receive HDLC controller
access to 64–byte HDLC FIFO in receive direction
controls the HDLC function when used on DS0
channels
controls the HDLC function when used on DS0
channels
Transmit HDLC Information register (THIR)
Transmit HDLC FIFO Register (THFR)
Transmit HDLC DS0 Control Register 1 (TDC1)
Transmit HDLC DS0 Control Register 2 (TDC2)
status information on transmit HDLC controller
access to 64–byte HDLC FIFO in transmit direction
controls the HDLC function when used on DS0
channels
controls the HDLC function when used on DS0
channels
相关PDF资料
PDF描述
DS21552G IC TXRX T1 1-CHIP 5V 100-BGA
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