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参数资料
| 型号： | DS2165QN+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC PROC ADPCM 16/24/32K 28-PLCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 500 |
| 类型： | ADPCM 处理器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.51x11.51） |
| 包装： | 带卷 (TR) |
DS2165Q
3 of 17
CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format, and channel coding for the
selected channel.
The X-side and Y-side PCM interfaces can be independently disabled (output tri-stated) by IPD. When
IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port
must not be operated faster than 39kHz.
ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST is cleared
by the device when the algorithm reset is complete.
Table 1. PIN DESCRIPTION
PIN
SYMBOL
TYPE
FUNCTION
2
RST
I
Reset. A high-low-high transition resets the algorithm. The device should be
reset on power-up and when changing to or from the hardware mode.
3
4
TM0
TM1
I
Test Modes 0 and 1. Connect to VSS for normal operation.
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
I
Address Select. A0 = LSB, A5 = MSB. Must match address/command word
to enable the serial port.
12
SPS
I
Serial Port Select. Connect to VDD to select the serial port; connect to VSS to
select the hardware mode.
13
MCLK
I
Master Clock. 10MHz clock for the ADPCM processing engine; may be
asynchronous to SCLK, CLKX, and CLKY.
14
VSS
—
Signal Ground. 0V
16
XIN
I
X Data In. Sampled on falling edge of CLKX during selected time slots.
17
CLKX
I
X Data Clock. Data clock for the X-side PCM interface; must be
synchronous with FSX.
18
FSX
I
X Frame Sync. 8kHz frame sync for the X-side PCM interface.
20
XOUT
O
X Data Output. Updated on rising edge of CLKX during selected time slots.
21
SCLK
I
Serial Data Clock. Used to write to the serial port registers.
22
SDI
I
Serial Data In. Data for on-board control registers; sampled on the rising
edge of SCLK. LSB sent first.
23
CS
I
Chip Select. Must be low to write to the serial port.
24
YOUT
O
Y Data Output. Updated on rising edge of CLKY during selected time slots.
25
FSY
I
Y Frame Sync. 8kHz frame sync for the Y-side PCM interface.
26
CLKY
I
Y Data Clock. Data clock for the Y-side PCM interface; must be
synchronous with FSY.
27
YIN
I
Y Data In. Sampled on falling edge of CLKY during selected time slots.
28
VDD
—
Positive Supply. 5.0V (3.0V for DS2165QL)
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| DS2167 | 功能描述:IC PROC ADPCM 16/24/32K 24-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 音频处理 系列:- 其它有关文件:STA321 View All Specifications 标准包装:1 系列:Sound Terminal™ 类型:音频处理器 应用:数字音频 安装类型:表面贴装 封装/外壳:64-LQFP 裸露焊盘 供应商设备封装:64-LQFP EP（10x10） 包装:Digi-Reel® 其它名称:497-11050-6 |
| DS2167N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Transcoder |
| DS2167Q | 功能描述:IC PROC ADPCM 16/24/32K 28-PLCC RoHS:否 类别:集成电路 (IC) >> 线性 - 音频处理 系列:- 其它有关文件:STA321 View All Specifications 标准包装:1 系列:Sound Terminal™ 类型:音频处理器 应用:数字音频 安装类型:表面贴装 封装/外壳:64-LQFP 裸露焊盘 供应商设备封装:64-LQFP EP（10x10） 包装:Digi-Reel® 其它名称:497-11050-6 |
| DS2167QN | 功能描述:IC PROC ADPCM 16/24/32K 28-PLCC RoHS:否 类别:集成电路 (IC) >> 线性 - 音频处理 系列:- 其它有关文件:STA321 View All Specifications 标准包装:1 系列:Sound Terminal™ 类型:音频处理器 应用:数字音频 安装类型:表面贴装 封装/外壳:64-LQFP 裸露焊盘 供应商设备封装:64-LQFP EP（10x10） 包装:Digi-Reel® 其它名称:497-11050-6 |
| DS2167QN/T&R | 制造商:Maxim Integrated Products 功能描述:IC PROC ADPCM 16/24/32K 28-PLCC |
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