参数资料
型号: DS2174Q+
厂商: Maxim Integrated Products
文件页数: 7/24页
文件大小: 0K
描述: IC BERT ENHANCED 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 26
功能: 增强型位误码率测试器(EBERT)
接口: E1,J1,T1
电路数: 1
电源电压: 3 V ~ 3.6 V
电流 - 电源: 50mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 管件
包括: 错误计数器,样式发生器和检测器
DS2174
15 of 24
3.2 Status Register
The status register contains information about the real-time status of the DS2174. When a particular event
has occurred, the appropriate bit in the register is set to a 1. All of the bits in this register (except for
SYNC) operate in a latched fashion, which means that if an event occurs and a bit is set to a 1, it remains
set until the user reads the register. For the BED, BCOF, and BECOF bits, they are cleared when read and
are not set again until the event has occurred again. For RLOS, RA0, and RA1 bits, they are cleared when
read if the condition no longer persists.
Status Register (Address = 4h)
(MSB)
(LSB)
RA1
RA0
BED
BECOF
BCOF
RLOS
SYNC
SYMBOL
FUNCTION
Not Assigned. Could be any value.
RA1
Receive All 1s. Set when 40 consecutive 1s are received in pseudorandom mode.
Allowed to be cleared when a 0 is received.
RA0
Receive All 0s. Set when 40 consecutive 0s are received in pseudorandom mode.
Allowed to be cleared when a 1 is received.
BED
Bit Error Detection. Set when bit error count is non-zero. Cleared when read.
BECOF
Bit Error Count Overflow. Set when the bit error counter overflows. Cleared when
read.
BCOF
Bit Counter Overflow. Set when the bit counter overflows. Cleared when read.
RLOS
Receive Loss-of-Sync. Set when the receiver is searching for synchronization.
Remains set until read once sync is achieved. This bit is latched.
SYNC
Sync. Real-time status of the synchronizer. This bit is not latched.
3.3 Pseudorandom Pattern Registers
Note: Bit 1 of Control Register 4 determines if the addresses point to the tap select or seed registers.
The tap select register is used to select the length and tap positions for pseudorandom
generation/reception. Each bit that is set to a 1 denotes a tap at that location for the feedback path. The
highest bit location set to a 1 is the length of the shift register. All pattern lengths are available in bit
mode, patterns 24 – 1 and greater are available in nibble mode, and patterns 28 – 1 and greater are
available in byte mode. The pattern generator generates all 1’s if the exponent in the polynomial is less
than 4 (nibble mode) or 8 (byte mode).
For example, to transmit/receive 215 – 1 (O.151) Bit14 and Bit13 would be set to a 1. All other bits would
be 0. Table 3-C gives tap select and seed values for many pseudorandom patterns. The seed value is
loaded into the transmit shift register on the rising edge of TL (CR1.0).
Tap Select/Seed Value Registers (Address = 5h–8h)
(MSB)
(LSB)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT23
BIT22
BIT21
BIT20
BIT19
BIT18
BIT17
BIT16
BIT31
BIT30
BIT29
BIT28
BIT27
BIT26
BIT25
BIT24
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