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参数资料
| 型号： | DS2176Q/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/15页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER RECEIVE T1 28-PLCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 500 |
| 类型： | 缓冲器 |
| Tx/Rx类型： | T1 |
| 延迟时间： | 100ns |
| 电容 - 输入： | 5pF |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 10mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.51x11.51） |
| 包装： | 带卷 (TR) |
DS2176
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PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
SIGN
I
Signaling Inhibit. When low, ABCD signaling updates are disabled for
a period determined by SM0 and SM1, or until returned high.
2
RMSYNC
I
Receive Multifram Sync. Must be pulsed high at multiframe
boundaries to establish frame and multiframe alignment.
3
RCLK
I
Receive Clock. Primary 1.544 MHz clock.
4
RSER
I
Receive Serial Data. Sampled on Falling edge of RCLK.
5
6
7
8
A
B
C
D
O
Robbed-Bit Signaling Outputs.
9
SCHCLK
O
System Channel Clock. Transitions high on channel boundaries; useful
for serial to parallel conversion of channel data.
10
11
SM0
SM1
I
Signaling Modes 0 and 1. Select signaling supervision technique.
12
VSS
–
Signal Ground. 0.0 volts.
13
S/ P
I
Serial/Parallel Select. Tie to VSS for parallel backplane applications, to
VDD for serial.
14
FMS
I
Frame Mode Select. Tie to VSS to select 193S(D4) framing to VDD for
193E (extended).
15
ALN
I
Align. Recenters buffer on next system side frame boundary when
forced low.
16
SFSYNC
I
System Frame Sync. Rising edge establishes start of frame.
17
SIGFRZ
O
Signaling Freeze. When high, indicates signaling updates have been
disabled internally via a slip or externally by forcing SIGH low.
18
SMSYNC
O
System Multiframe Sync. Slip-compensated multiframe output;
indicates when signaling updates are made.
19
SBIT8
O
System Bit 8. High during the LSB time of each channel. Used to
reinsert extracted signaling into outgoing data stream.
20
SLIP
O
Frame Slip. Active low, open collector output. Held low for 65
SYSCLK cycles when a slip occurs.
21
SSER
O
System Serial Out. Updated on rising edge of SYSCLK.
22
SYSCLK
I
System Clock. 1.544 or 2.048 MHz data clock.
23
SCLKSEL
I
System Clock Select. Tie to VSS for 1.544 MHz applications, to VDD for
2.048 MHz.
24
VDD
–
Positive Supply. 5.0 volts.
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