参数资料
型号: DS2176QN/T&R
厂商: Maxim Integrated Products
文件页数: 11/15页
文件大小: 0K
描述: IC BUFFER RECEIVE T1 IND 28-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
类型: 缓冲器
Tx/Rx类型: T1
延迟时间: 100ns
电容 - 输入: 5pF
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 10mA
安装类型: 表面贴装
封装/外壳: 28-LCC(J 形引线)
供应商设备封装: 28-PLCC(11.51x11.51)
包装: 带卷 (TR)
DS2176
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passed through the receive buffer and presented at SSER immediately after the rising edge of the system
side frame sync. The F–bit is dropped in 2.048 MHz applications and the MSB of channel 1 appears at
SSER one bit period after a rising edge at SFSYNC. SSER is forced to 1 in all channels greater than 24.
See Figures 3 and 4.
In 2.048 MHz applications (SCLKSEL=1), the PCM buffer control logic establishes slip criteria different
from that used in 1.544 MHz applications to compensate for the faster system-side read frequency.
PARALLEL COMPATIBILITY
The DS2176 is compatible with parallel and serial back-planes. Channel 1 data appears at SSER after a
rising edge at SFSYNC as shown in Figures 3 and 4 (serial applications, S/ P =1). The device utilizes a
look–ahead circuit in parallel applications (S/ P =0). Data is output 8 clocks earlier, allowing the user to
convert parallel data eternally.
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 3
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