参数资料
型号: DS2180A+
厂商: Maxim Integrated Products
文件页数: 11/35页
文件大小: 0K
描述: IC TRANSCEIVER T1 40-DIP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 10
功能: 收发器
接口: T1
电路数: 1
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 3mA
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 40-DIP(0.600",15.24mm)
供应商设备封装: 40-PDIP
包装: 管件
包括: 警报生成和检测,B7 填充模式,B8ZS 模式,错误检测和计数器,“硬件”模式,透明模式
产品目录页面: 1429 (CN2011-ZH PDF)
DS2180A
19 of 35
RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 18
(MSB)
(LSB)
BVCS
ECS
RYEL
RCL
FERR
B8ZSD
RBL
RLOS
SYMBOL
POSITION
NAME AND DESCRIPTION
BVCS
RIMR.7
Bipolar Violation Count Saturation Mask.
1 = Interrupt masked.
0 = Interrupt masked.
ECS
RIMR.6
Error Count Saturation Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RYEL
RIMR.5
Receive Yellow Alarm Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RCL
RIMR.4
Receive Carrier Loss Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
FERR
RIMR.3
Frame Bit Error Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
B8ZSD
RIMR.2
B8ZS Detect Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RBL
RIMR.1
Receive Blue Alarm Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RLOS
RIMR.0
Receive Loss of Sync Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
ALARM COUNTERS
The three onboard alarm event counters allow the transceiver to monitor and record error events without
processor intervention on each event occurrence. All of these counters are presettable by the user
establishing an event count interrupt threshold. As each counter saturates, the next error event occurrence
will set a bit in the RSR and generate an interrupt unless masked. The user may read these registers at any
time; in many systems, the host will periodically poll these registers to establish link error rate
performance.
OOF EVENTS AND ERRORED
SUPERFRAMES
Out of frame is declared when at least two of four (or five) consecutive framing bits are in error. FT bits
are tested for OOF occurrence in 193S; the FPS bits are tested in 193E. OOF events are recorded by the
4-bit OOF counter in the error counter register. In the 193E framing mode, the OOF event is logically
OR’ed with an on-chip generated CRC checksum. This event, known as errored superframe, is recorded
by the 4-bit ESF error counter in the error count register. In the 193S framing mode, the 4-bit ESF error
counter records individual FT and FS errors when RCR.3=1 or FT errors only when RCR.3=0.
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