参数资料
型号: DS2181AN
厂商: Maxim Integrated Products
文件页数: 8/32页
文件大小: 0K
描述: IC TXRX CEPT PRIM RATE IND 40DIP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 10
类型: 收发器
驱动器/接收器数: 1/1
规程: CEPT
电源电压: 4.5 V ~ 5.5 V
安装类型: 通孔
封装/外壳: 40-DIP(0.600",15.24mm)
供应商设备封装: 40-PDIP
包装: 管件
DS2181A
16 of 32
TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 13
NOTES:
1. Low-high transitions on TMSYNC and/or TFSYNC must occur one TCLK period early with respect
to actual frame and multiframe boundaries. TMO follows the rising edge of TMSYNC or TFSYNC.
2. TAF transitions on true frame boundaries.
3. Delay from TSER to TPOS, TNEG is five TCLK periods.
TRANSMIT SIGNALING TIMESLOT TIMING Figure 14
RECEIVE SIGNALING
Receive signaling data is available at two outputs: RSER and RSD. RSER outputs the signaling data in
timeslot 16 at RSER. The signaling data is also extracted from timeslot 16 and presented at RSD during
the timeslots shown in Table 7. This channel-associated signaling simplifies CAS system design.
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