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参数资料
| 型号： | DS2186S |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC TRANSMIT LINE INTERFC 20-SOIC |
| 标准包装： | 37 |
| 类型： | 线路驱动器，发射器 |
| 驱动器/接收器数： | 1/0 |
| 规程： | T1/CEPT |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
DS2186
022798 3/11
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
TAIS
I
Transmit Alarm Indication Signal. When high, output data is
forced to all ones at the TCLK (LB=0) or LCLK (LB=1) rate.
2
ZCSEN
I
Zero Code Suppression Enable. When high, B8ZS or HDB3
encoder enabled.
3
TCLKSEL
I
Transmit Clock Select. Tie to VSS for 1.544 MHz (T1) applica-
tions, to VDD for 2.048 MHz (CEPT) applications.
4
5
6
LEN0
LEN1
LEN2
I
Length Select 0, 1 and 2. State determines output T1 waveform
shape and characteristics.
7
VDD
–
Positive Supply. 5.0 volts.
8
9
TTIP,
TRING
O
Transmit Tip and Ring. Line driver outputs; connect to transmit
line transformer.
10
VSS
–
Signal Ground. 0.0 volts.
11
LF
O
Line Fault. Open collector active low output. Held low during an
output driver fault and/or failure; tri–stated otherwise.
12
13
MRING,
MTIP
I
Monitor Tip and Ring. Normally connected to TTIP and TRING.
Sense inputs for line fault detection circuitry.
14
LB
I
Loopback. When high, input data is sampled at LPOS and LNEG
on falling edges of LCLK; when low, input data is sampled at TPOS
and TNEG on falling TCLK.
15
16
TNEG,
TPOS
I
Transmit Data. Sampled on falling edges of TCLK when LB=0.
17
TCLK
I
Transmit Clock. 1.544 MHz or 2.048 MHz primary data clock.
18
19
LNEG,
LPOS
I
Loopback Data. Sampled on falling edges of LCLK when LB=1.
20
LCLK
I
Loopback Clock. 1.544 MHz or 2.048 MHz loopback data clock.
INPUT DATA MODES
Input data is sampled on the falling edge of TCLK or
LCLK and can be bipolar (dual rail) or unipolar (single
rail, NRZ). TPOS, TNEG and TCLK are the data and
clock inputs when LB=0, LPOS, LNEG and LCLK when
LB=1. TPOS and TNEG (LPOS and LNEG) must be tied
together in NRZ applications.
ZERO CODE SUPPRESSION MODES
Transmitted data is treated transparently (no zero code
suppression) when ZCSEN=0. HDB3 code words re-
place any all–zero nibble when ZCSEN=1 and
TCLKSEL=1. B8ZS code words replace any incoming
all–zero byte when ZCSEN=1 and TCLKSEL=0.
ALARM INDICATION SIGNAL
When TAIS is set, an all ones code is continuously
transmitted at the TCLK rate (LB=0) or the LCLK rate
(LB=1).
WAVE SHAPING
The device supports T1 short loop (DSX–1; 0 to 655
feet), T1 long loop (CSU; 0 dB, –7.5 dB and –15 dB) and
CEPT (CCITT G.703) pulse template requirements.
On–chip laser trimmed delay lines clocked by either
TCLK or LCLK control a precision digital–to–analog
converter to build the desired waveforms, which are
buffered differentially by the line drivers.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2186S/T&R | 制造商:Maxim Integrated Products 功能描述:TRANSMIT LINE INTERFACE SOIC TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TRANSMIT LINE INTERFC 20-SOIC |
| DS2186S/T&R | 功能描述:IC TRANSMIT LINE INTERFC 20-SOIC RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| DS2186S+ | 功能描述:网络控制器与处理器 IC Transmit Line Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2186SN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CEPT/T1 Interface |
| DS2187 | 功能描述:网络控制器与处理器 IC Receive Line Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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