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参数资料
| 型号： | DS2187S+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/10页 |
| 文件大小： | 0K |
| 描述： | IC RECEIVE LINE INTERFACE 20SOIC |
| 标准包装： | 37 |
| 功能： | 接收线路接口 |
| 接口： | T1 |
| 电路数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 18mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
| 包括： | AMI / B8ZS / HDB3 编码信号解码器 |
DS2187
2 of 10
DS2187 BLOCK DIAGRAM Figure 1
LINE INPUT
Input signals are coupled to the DS2187 via a 1:2 center-tapped transformer as shown in Figure 2. For T1
applications, R1 and R2 must be 200 ohms in order to properly terminate the line at 100 ohms. R1 and R2
are set at 150 or 240 ohms for CEPT applications. Special internal circuitry of the RTIP and RRING
inputs permits negative signal excursions below VSS, which will occur in the circuit in Figure 2.
PEAK DETECTOR AND SLICERS
Signal pulses present at RTIP and RRING are sampled by an internal peak detect circuit. The clock and
data slicer threshold are set for 50% of the sampled peak voltage.
Peak input levels at RRIP and RRING must exceed 0.6 volts to establish minimum slicer thresholds.
Signals below this level will cause RCL to transition high after 192 bit times.
CLOCK EXTRACTION
The DS2187 utilizes both frequency locked (FLL) and digital phase locked (DPLL) loops to recover data
and clock from the incoming AMI signal. T1 applications utilize a 18.528 MHz clock divided by either
11, 12, or 13 to match the phase of the incoming jittered line signal. This technique affords exceptional
jitter tracking which enables the DS2187 to meet the latest AT&T TR 62411 and ECSA jitter
specifications. A 24.576 MHz clock divided by 11, 12, or 13 provides jitter tracking in the CEPT mode.
The DPLL output is buffered and presented at RCLK. An on-chip, laser-trimmed, voltage-controlled
oscillator (VCO) provides the precision 18.528 MHz and 24.576 MHz frequency sources utilized in the
FLL. The FLL is a high-Q circuit which tracks the average frequency of the incoming signal, minimizing
the effect of the DPLL on output jitter.
During the acquisition time or if RCL goes high, the LOCK pin will go low to indicate a loss of
synchronization to the line signal. Once this pin goes high, the FLL has achieved frequency lock and
valid data is present at the RPOS and RNEG outputs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2187S/T&R | 制造商:Maxim Integrated Products 功能描述:IC RECEIVE LINE INTERFACE 20SOIC |
| DS2187S/T&R | 功能描述:网络控制器与处理器 IC Receive Line Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2187S+ | 功能描述:网络控制器与处理器 IC Receive Line Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2188 | 功能描述:通信集成电路 - 若干 RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
| DS2188+ | 功能描述:通信集成电路 - 若干 RoHS:否 制造商:Maxim Integrated 类型:Transport Devices 封装 / 箱体:TECSBGA-256 数据速率:100 Mbps 电源电压-最大:1.89 V, 3.465 V 电源电压-最小:1.71 V, 3.135 V 电源电流:50 mA, 225 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Tube |
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