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参数资料
型号： DS21FT42N
厂商： Maxim Integrated Products
文件页数： 47/114页
文件大小： 0K
描述： IC FRAMER T1 4X3 12CH IND 300BGA
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 40
控制器类型： T1 调帧器
接口： 并行/串行
电源电压： 2.97 V ~ 3.63 V
电流 - 电源： 225mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 300-BBGA
供应商设备封装： 300-PBGA（27x27）
包装： 管件
DS21FT42/DS21FF42
38 of 114
SYMBOL
POSITION
NAME AND DESCRIPTION
TESMDM
CCR3.0
Transmit Elastic Store Minimum Delay Mode. See
Section 17 for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
PULSE DENSITY ENFORCER
The Framer always examines both the transmit and receive data streams for violations of the following
rules which are required by ANSI T1.403:
– No more than 15 consecutive zeros
– At least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively. When the CCR3.3 is set to one, the DS21Q42 will force the transmitted stream to meet this
requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should
be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB)
(LSB)
RSRE
RPCSI
RFSA1
RFE
RFF
THSE
TPCSI
TIRFS
SYMBOL
POSITION
NAME AND DESCRIPTION
RSRE
CCR4.7
Receive Side Signaling Re–Insertion Enable. See Section
14 for details.
0 = do not re-insert signaling bits into the data stream
presented at the RSER pin
1 = reinsert the signaling bits into data stream presented at
the RSER pin
RPCSI
CCR4.6
Receive Per–Channel Signaling Insert. See Section 14 for
more details.
0 = do not use RCHBLK to determine which channels should
have signaling re–inserted
1 = use RCHBLK to determine which channels should have
signaling re–inserted
RFSA1
CCR4.5
Receive Force Signaling All Ones. See Section 14 for more
details.
0 = do not force extracted robbed–bit signaling bit positions
to a one
1 = force extracted robbed–bit signaling bit positions to a one
RFE
CCR4.4
Receive Freeze Enable. See Section 14 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and
RSER if CCR4.7 = 1).
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