参数资料
型号: DS21FT44+
厂商: Maxim Integrated Products
文件页数: 87/117页
文件大小: 0K
描述: IC FRAMER 4X4 16CH 300-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: E1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 225mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 300-BBGA
供应商设备封装: 300-PBGA(27x27)
包装: 管件
DS21FT44/DS21FF44
71 of 117
Table 19-1. HDLC CONTROLLER REGISTER LIST
NAME
FUNCTION
HDLC Control Register (HCR)
General control over the HDLC controller
HDLC Status Register (HSR)
Key status information for both transmit and receive
directions
HDLC Interrupt Mask Register (HIMR)
Allows/stops status bits to/from causing an interrupt
Receive HDLC Information Register
(RHIR)
Status information on receive HDLC controller
Receive HDLC FIFO Register (RHFR)
Access to 64-byte HDLC FIFO in receive direction
Receive HDLC DS0 Control Register 1
(RDC1)
Receive HDLC DS0 Control Register 2
(RDC2)
Controls the HDLC function when used on DS0 channels
Transmit HDLC Information Register
(THIR)
Status information on transmit HDLC controller
Transmit HDLC FIFO Register (THFR)
Access to 64–byte HDLC FIFO in transmit direction
Transmit HDLC DS0 Control Register 1
(TDC1)
Transmit HDLC DS0 Control Register 2
(TDC2)
Controls the HDLC function when used on DS0 channels
19.2. HDLC Status Registers
Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be
set to a one. Some of the bits in these three status registers are latched and some are real time bits that are
not latched. Section 19.4 contains register descriptions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred
again. The real time bits report the current instantaneous conditions that are occurring and the history of
these bits is not latched.
Like the other status registers in the framer, the user will always proceed a read of any of the three
registers with a write. The byte written to the register will inform the framer which of the latched bits the
user wishes to read and have cleared (the real time bits are not affected by writing to the status register).
The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read
and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with current value and it will be cleared. When a
zero is written to a bit position, the read register will not be updated and the previous value will be held.
A write to the status and information registers will be immediately followed by a read of the same
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