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参数资料
| 型号： | DS21Q348 |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/76页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 3.3V 144BGA |
| 标准包装： | 90 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BBGA |
| 供应商设备封装： | 144-PBGA（17x17） |
| 包装： | 管件 |
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DS21348/DS21Q348
19 of 76
NAME
PIN
I/O
FUNCTION
MCLK
30
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional. G.703 requires an accuracy of
±50ppm for
both T1 and E1. TR62411 and ANSI specs require an accuracy of
±32ppm for T1 interfaces.
MM0/MM1
18/19
I
Monitor Mode Select Bits 0 and 1 [H/W Mode]. These inputs
determine if the receive equalizer is in a monitor mode (Table 2-11).
NA
—
I
Not Assigned. Should be tied low.
NRZE
3
I
NRZ Enable [H/W Mode]
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
PBEO
24
O
PRBS Bit Error Output. The receiver will constantly search for a
QRSS (T1) or a 215-1 (E1) PRBS depending whether T1 or E1
mode is selected. Remains high if out of synchronization with the
PRBS pattern. Goes low when synchronized to the PRBS pattern.
Any errors in the received pattern after synchronization will cause a
positive going pulse (with same period as E1 or T1 clock)
synchronous with RCLK.
RCLK
40
O
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RCL
25
O
Receive Carrier Loss. An output which will toggle high during a
receive carrier loss.
RNEG
39
O
Receive Negative Data. Updated on the rising edge (CES = 0) or
the falling edge (CES = 1) of RCLK with the bipolar data out of the
line interface. Set NRZE to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RPOS
38
O
Receive Positive Data. Updated on the rising edge (CES = 0) or the
falling edge (CES = 1) of RCLK with bipolar data out of the line
interface. Set NRZE pin to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
section 6.4 for details.
RT0/RT1
44/23
I
Receive LIU Termination Select Bits 0 and 1 [H/W Mode]. These
inputs determine the receive termination. See Table 2-12.
RTIP/
RRING
27/28
I
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 5
for details.
SCLKE
4
I
Receive and Transmit Synchronization Clock Enable
0 = disable 2.048MHz synchronization transmit and receive mode
1 = enable 2.048 Hz synchronization transmit and receive mode
TCLK
43
I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21Q348B | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q348DK | 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS21Q348N | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q348NB | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q348-W | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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