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参数资料
| 型号： | DS21Q348N |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Interface |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PBGA144 |
| 封装： | BGA-144 |
| 文件页数： | 3/67页 |
| 文件大小： | 339K |
| 代理商： | DS21Q348N |
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DS21348/Q348
11 of 67
Table 4-3 PIN DESCRIPTIONS (Sorted by Pin Name, DS21348T Pin Numbering)
Acronym
Pin
I/O
Description
A0
To
A4
11
to
7
I
Address Bus. In non-multiplexed bus operation (BIS1 = 0, BIS0 =
1), serves as the address bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), these pins are not used and should be tied low.
ALE
(AS)
4I
Address Latch Enable (Address Strobe). When using the parallel
port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In non-multiplexed
bus mode (BIS0 = 1), should be tied low.
BIS0/
BIS1
32/
33
I
Bus Interface Select Bits 0 & 1. Used to select bus interface
option. See Table 4-1 for details.
BPCLK
31
O
Back Plane Clock. A 16.384 MHz, 8.192 MHz, 4.096 MHz, or
2.048 MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384 MHz
output.
CES
12
I
Receive & Transmit Clock Edge Select. Selects which RCLK
edge to update RPOS and RNEG and which TCLK edge to sample
TPOS and TNEG. CES combines TCES (CCR2.1) and RCES
(CCR2.0)
0 = update RNEG/RPOS on rising edge of RCLK; sample
TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample
TPOS/TNEG on rising edge of TCLK
CS*
1
I
Chip Select. Must be low to read or write to the device. CS* is an
active low signal.
D0 / AD0
To
D7 / AD7
19
to
12
I/O
Data Bus / Address/Data Bus. In non-multiplexed bus operation
(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
DJA
8I
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
EGL
1I
Receive Equalizer Gain Limit. This bit controls the sensitivity of
the receive equalizer. See Table 4-6.
ETS
2I
E1/T1 Select.
0 = E1
1 = T1
HBE
11
I
Receive & Transmit HDB3/B8ZS Enable. HBE combines RHBE
(CCR2.3) and THBE (CCR2.2).
0 = enable HDB3 (E1) / B8ZS (T1)
1 = disable HDB3 (E1) / B8ZS (T1)
HRST*
29
I
Hardware Reset. Bringing HRST* low will reset the DS21348
setting all control bits to their default state of all zeros.
ICES
8I
Input Clock Edge Select. Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
INT*
23
O
Interrupt [INT*] pin 23. Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
相关PDF资料 |
PDF描述 |
|---|---|
| DS21Q348 | DATACOM, PCM TRANSCEIVER, PBGA144 |
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| DS21352LN | DATACOM, PCM TRANSCEIVER, PQFP100 |
| DS21552L | DATACOM, PCM TRANSCEIVER, PQFP100 |
| DS21552LN | DATACOM, PCM TRANSCEIVER, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21Q348NB | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q348-W | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q352 | 功能描述:网络控制器与处理器 IC 3.3/5V Quad T1/E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q352B | 功能描述:网络控制器与处理器 IC 3.3/5V Quad T1/E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q352B+ | 功能描述:网络控制器与处理器 IC 3.3/5V Quad T1/E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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