参数资料
型号: DS21Q348N
厂商: Maxim Integrated Products
文件页数: 41/76页
文件大小: 0K
描述: IC LIU T1/E1/J1 QUAD 3.3V 144BGA
标准包装: 90
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 144-BBGA
供应商设备封装: 144-PBGA(17x17)
包装: 管件
DS21348/DS21Q348
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6.2 Loopbacks
6.2.1 Remote Loopback (RLB)
When RLB (CCR6.6) is enabled, the DS21348 is placed into remote loopback. In this loopback, data
from the clock/data recovery state machine will be looped back to the transmit path passing through the
jitter attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented
at TPOS and TNEG will be ignored. See Figure 1-1 for details.
If the Automatic Remote Loop Back Enable (CCR6.5) is set to a one, the DS21348 will automatically go
into remote loop back when it detects the loop-up code programmed in the Receive Up Code Definition
Registers (RUPCD1 and RUPCD2) for a minimum of 5 seconds. When the DS21348 detects the loop
down code programmed in the Receive Loop-Down Code Definition registers (RDNCD1 and RDNCD2)
for a minimum of 5 seconds, the DS21348 will come out of remote loop back. The ARLB can also be
disabled by setting ARLBE to a zero.
6.2.2 Local Loopback (LLB)
When LLB (CCR6.7) is set to a one, the DS21348 is placed into Local Loopback. In this loopback, data
on the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through
the jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at
RTIP and RRING will be ignored. If Transmit Unframed All Ones (CCR3.7) is set to a one while in LLB,
TTIP and TRING will transmit all ones while TCLK and TPOS/TNEG will be looped back to RCLK and
RPOS/RNEG. See Figure 1-1 for more details.
6.2.3 Analog Loopback (ALB)
Setting ALB (CCR6.4) to a one puts the DS21348 in Analog Loopback. Signals at TTIP and TRING will
be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored.
The signals at TTIP and TRING will be transmitted as normal. See Figure 1-1 for more details.
6.2.4 Dual Loopback (DLB)
Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS21348 into Dual
Loopback operation. The TCLK and TPOS/TNEG signals will be looped back through the jitter
attenuator (if enabled) and output at RCLK and RPOS/RNEG. Clock and data recovered from RTIP and
RRING will be looped back to the transmit-side and output at TTIP and TRING. This mode of operation
is not available when implementing hardware operation. See Figure 1-1 for more details.
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