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参数资料
| 型号： | DS21Q354DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN FOR DS21Q354 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 电信，调帧器和线路接口装置（LIU） |
| 已用 IC / 零件： | DS21Q354 |
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
December 29, 1998
7
A17
DVSS2
–
Digital Signal Ground.
A20
DVSS2
–
Digital Signal Ground.
B11
DVSS2
–
Digital Signal Ground.
C13
DVSS2
–
Digital Signal Ground.
A5
DVSS3
–
Digital Signal Ground.
B7
DVSS3
–
Digital Signal Ground.
B9
DVSS3
–
Digital Signal Ground.
C3
DVSS3
–
Digital Signal Ground.
H20
DVSS4
–
Digital Signal Ground
L20
DVSS4
–
Digital Signal Ground
N17
DVSS4
–
Digital Signal Ground
U13
DVSS4
–
Digital Signal Ground
U1
INT*
O
Interrupt for all four SCTs.
Y15
JTCLK
I
JTAG Clock.
N1
JTDI
I
JTAG Data Input.
H18
JTDO2
O
JTAG Data Output from SCT2.
V17
JTDO3
O
JTAG Data Output from SCT3.
V19
JTDO4
O
JTAG Data Output from SCT4.
W13
JTMS
I
JTAG Test Mode Select.
V18
JTRST*
I
JTAG Reset.
K2
LIUC
I
Line Interface Connect for all Four SCTs.
T1
MCLK1
I
Master Clock for SCT1 and SCT3.
W20
MCLK2
I
Master Clock for SCT2 and SCT4.
U10
MUX
I
Mux Bus Select.
M2
RCHBLK1
O
Receive Channel Block for SCT1.
G17
RCHBLK2
O
Receive Channel Block for SCT2.
G4
RCHBLK3
O
Receive Channel Block for SCT3.
Y12
RCHBLK4
O
Receive Channel Block for SCT4.
J1
RCHCLK1
O
Receive Channel Clock for SCT1.
D14
RCHCLK2
O
Receive Channel Clock for SCT2.
F3
RCHCLK3
O
Receive Channel Clock for SCT3.
U14
RCHCLK4
O
Receive Channel Clock for SCT4.
N3
RCLK1
O
Receive Clock Output from the Framer on SCT1.
B13
RCLK2
O
Receive Clock Output from the Framer on SCT2.
E3
RCLK3
O
Receive Clock Output from the Framer on SCT3.
M18
RCLK4
O
Receive Clock Output from the Framer on SCT4.
M4
RCLKI1
I
Receive Clock Input for the LIU on SCT1.
A15
RCLKI2
I
Receive Clock Input for the LIU on SCT2.
A4
RCLKI3
I
Receive Clock Input for the LIU on SCT3.
R17
RCLKI4
I
Receive Clock Input for the LIU on SCT4.
M3
RCLKO1
O
Receive Clock Output from the LIU on SCT1.
C14
RCLKO2
O
Receive Clock Output from the LIU on SCT2.
B4
RCLKO3
O
Receive Clock Output from the LIU on SCT3.
T17
RCLKO4
O
Receive Clock Output from the LIU on SCT4.
N2
RD*(DS*)
I
Read Input (Data Strobe)
K4
RFSYNC1
O
Receive Frame Sync (before the receive elastic store) for SCT1.
D17
RFSYNC2
O
Receive Frame Sync (before the receive elastic store) for SCT2.
A2
RFSYNC3
O
Receive Frame Sync (before the receive elastic store) for SCT3.
V14
RFSYNC4
O
Receive Frame Sync (before the receive elastic store) for SCT4.
F1
RLCLK1
O
Receive Link Clock for SCT1.
A12
RLCLK2
O
Receive Link Clock for SCT2.
D3
RLCLK3
O
Receive Link Clock for SCT3.
K18
RLCLK4
O
Receive Link Clock for SCT4.
G2
RLINK1
O
Receive Link Data for SCT1.
A13
RLINK2
O
Receive Link Data for SCT2.
A3
RLINK3
O
Receive Link Data for SCT3.
U12
RLINK4
O
Receive Link Data for SCT4.
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