参数资料
型号: DS21Q43AT
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封装: TQFP-128
文件页数: 11/60页
文件大小: 748K
代理商: DS21Q43AT
DS21Q43A
19 of 60
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB)
(LSB)
FLB
THDB3
TG802
TCRC4
RSM
RHDB3
RG802
RCRC4
SYMBOL
POSITION
NAME AND DESCRIPTION
FLB
CCR1.7
Framer Loopback.
0=loopback disabled
1=loopback enabled
THDB3
CCR1.6
Transmit HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
TG802
CCR1.5
Transmit G.802 Enable. See Section 11 for details.
0=do not force TCHBLK high during bit 1 of timeslot 26
1=force TCHBLK high during bit 1 of timeslot 26
TCRC4
CCR1.4
Transmit CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
RSM
CCR1.3
Receive Signaling Mode Select.
0=CAS signaling mode
1=CCS signaling mode
RHDB3
CCR1.2
Receive HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
RG802
CCR1.1
Receive G.802 Enable. See Section 11 for details.
0=do not force RCHBLK high during bit 1 of timeslot 26
1=force RCHBLK high during bit 1 of timeslot 26
RCRC4
CCR1.0
Receive CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
FRAMER LOOPBACK
When CCR1.7 is set to a 1, the DS21Q43A will enter a Framer LoopBack (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS21Q43A will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1. data will be transmitted as normal at TPOS and TNEG
2. data at RPOS and RNEG will be ignored
3. the receive side signals become synchronous with TCLK instead of RCLK.
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