参数资料
型号: DS21Q44T
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封装: TQFP-128
文件页数: 14/105页
文件大小: 702K
代理商: DS21Q44T
DS21Q44
16 of 105
RECEIVE SIDE PINS
Signal Name:
RLINK
Signal Description:
Receive Link Data
Signal Type:
Output
Updated with full recovered E1 data stream on the rising edge of RCLK.
Signal Name:
RLCLK
Signal Description:
Receive Link Clock
Signal Type:
Output
A 4 kHz to 20-kHz clock for the RLINK output. Used for sampling Sa bits.
Signal Name:
RCLK
Signal Description:
Receive Clock Input
Signal Type:
Input
2.048 MHz clock that is used to clock data through the receive side framer.
Signal Name:
RCHCLK
Signal Description:
Receive Channel Clock
Signal Type:
Output
A 256-kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS =
1 (DS21Q43 emulation).
Signal Name:
RCHBLK
Signal Description:
Receive Channel Block
Signal Type:
Output
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps service,
768 kbps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
Signal Name:
RSER
Signal Description:
Receive Serial Data
Signal Type:
Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:
RSYNC
Signal Description:
Receive Sync
Signal Type:
Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC
multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
相关PDF资料
PDF描述
DS21Q44TN DATACOM, FRAMER, PQFP128
DS21Q48N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q48 DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q552 DATACOM, PCM TRANSCEIVER, PBGA256
DS2250-32-16 8-BIT, 16 MHz, MICROCONTROLLER, SMA40
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