参数资料
型号: DS21Q44T
厂商: Maxim Integrated Products
文件页数: 17/105页
文件大小: 0K
描述: IC FRAMER ENHANCED E1 4X 128TQFP
标准包装: 72
控制器类型: E1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
DS21Q44
19 of 105
Signal Name:
BTS
Signal Description:
Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name:
RD* (DS*)
Signal Description:
Read Input (Data Strobe)
Signal Type:
Input
RD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing
diagrams in section 19 .
Signal Name:
FS0 AND FS1
Signal Description:
Framer Selects
Signal Type:
Input
Selects which of the four framers to be accessed.
Signal Name:
CS*
Signal Description:
Chip Select
Signal Type:
Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name:
WR* (R/W*)
Signal Description:
Write Input (Read/Write)
Signal Type:
Input
WR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name:
TEST
Signal Description:
3–State Control
Signal Type:
Input
Set high to 3–state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board level testing.
Signal Name:
JTRST
Signal Description:
IEEE 1149.1 Test Reset
Signal Type:
Input
If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally.
If FMS = 0: JTAG functionality is available and JTRST is pulled up internally by a 10=kilo ohm resistor.
If FMS = 0, and boundary scan is not used this pin should be held low. This signal is used to
asynchronously reset the test access port controller. The device enters the DEVICE ID MODE when
JTRST is pulled high. The device enters the DEVICE ID MODE when JTRST is pulled high. The
device operates as a T1/E1 transceiver if JTRST is pulled low.
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