参数资料
型号: DS2405Z/T&R
厂商: Maxim Integrated Products
文件页数: 3/15页
文件大小: 0K
描述: IC SWITCH ADDRESS NCH O-D SOT223
标准包装: 2,500
接口: 1 线
电源电压: 2.8 V ~ 6 V
封装/外壳: TO-261-4,TO-261AA
供应商设备封装: SOT-223-3
包装: 带卷 (TR)
安装类型: 表面贴装
DS2405
11 of 15
Skip ROM [CCh]
The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Skip ROM command.
Since the DS2405 contains only the 64-bit ROM with no additional data fields, the Skip ROM is not
applicable and will cause no further activity on the 1-Wire bus if executed. The DS2405 does not interfere
with other 1-Wire parts on a multidrop bus that do respond to a Skip ROM (for example, a DS2405 and
DS1994 on the same bus).
1-WIRE SIGNALING
The DS2405 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data.
All these signals except Presence Pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2405 is shown in Figure 5.
A Reset Pulse followed by a Presence Pulse indicates the DS2405 is ready to send or receive data given
the correct ROM command.
The bus master transmits (TX) a Reset Pulse (tRSTL, minimum 480μs). The bus master then releases the
line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the 5k
Ω pullup resistor.
After detecting the rising edge on the data pin, the DS2405 waits (tPDH, 15-60μs) and then transmits the
Presence Pulse (tPDL, 60-240μs).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
480
μs ≤ tRSTL < ∞*
480
μs ≤ tRSTH< ∞ (includes recovery time)
15
μs ≤ tPDH< 60μs
60
μs ≤ tPDL< 240μs
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960
μs.
RESISTOR
MASTER
DS2405
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