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参数资料
| 型号： | DS2431P-A1+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 17/27页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1KBIT 6TSOC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 4,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1K（256 x 4） |
| 接口： | 1 线 串行 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 6-LSOJ |
| 供应商设备封装： | 6-TSOC |
| 包装： | 带卷 (TR) |
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DS2431
1024-Bit, 1-Wire EEPROM
V PUP
V IHMASTER
V TH
V TL
V ILMAX
MASTER Tx "RESET PULSE"
ε
t MSP
MASTER Rx "PRESENCE PULSE"
0V
t RSTL
t PDH
t PDL
t REC
t F
t RSTH
RESISTOR
Figure 10. Initialization Procedure: Reset and Presence Pulse
MASTER
DS2431
Read/Write Time Slots
Data communication with the DS2431 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 11 illus-
trates the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold V TL , the DS2431 starts its internal
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the V TH threshold before the write-
one low time t W1LMAX is expired. For a write-zero time
slot, the voltage on the data line must stay below the
V TH threshold until the write-zero low time t W0LMIN is
expired. For the most reliable communication, the volt-
age on the data line should not exceed V ILMAX during
the entire t W0L or t W1L window. After the V TH threshold
has been crossed, the DS2431 needs a recovery time
t REC before it is ready for the next time slot.
Maxim Integrated
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V TL
until the read low time t RL is expired. During the t RL
window, when responding with a 0, the DS2431 starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS2431 does not hold the data line low at all, and the
voltage starts rising as soon as t RL is over.
The sum of t RL + δ (rise time) on one side and the inter-
nal timing generator of the DS2431 on the other side
define the master sampling window (t MSRMIN to
t MSRMAX ), in which the master must perform a read
from the data line. For the most reliable communication,
t RL should be as short as permissible, and the master
should read close to but no later than t MSRMAX . After
reading from the data line, the master must wait until
t SLOT is expired. This guarantees sufficient recovery
time t REC for the DS2431 to get ready for the next time
slot. Note that t REC specified herein applies only to a
single DS2431 attached to a 1-Wire line. For multide-
vice configurations, t REC must be extended to accom-
modate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482-
x00 or DS2480B 1-Wire line drivers can be used.
17
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2431P-S26+T | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel 制造商:Maxim Integrated Products 功能描述:1-WIRE EEPROM 1KB TSOC |
| DS2431Q R | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1024-Bit, 1-Wire EEPROM |
| DS2431Q T | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1024-Bit, 1-Wire EEPROM |
| DS2431Q+R | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1024-Bit, 1-Wire EEPROM Individual Memory Pages Can Be Permanently |
| DS2431Q+T | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1024-Bit, 1-Wire EEPROM Individual Memory Pages Can Be Permanently |
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