DS2450
7 of 24
102199
WRITE MEMORY [55H]
The Write Memory command is used to write to memory pages 1 and 2 in order to set the channel-
specific control data and alarm thresholds. The bus master will follow the command byte with a two byte
starting address (TA1=(T7:T0), TA2=(T15:T8)) and a data byte of (D7:D0). A 16-bit CRC of the
command byte, address bytes, and data byte is computed by the DS2450 and read back by the bus master
to confirm that the correct command word, starting address, and data byte were received. Now the
DS2450 copies the data byte to the specified memory location. With the next eight time slots the bus
master receives a copy of the same byte but read from memory for verification. If the verification fails, a
Reset Pulse should be issued and the current byte address should be written again.
If the bus master does not issue a Reset Pulse and the end of memory was not yet reached, the DS2450
will automatically increment its address counter to address the next memory location. The new two-byte
address will also be loaded into the 16-bit CRC-generator as a starting value. The bus master will send
the next byte using eight write time slots. As the DS2450 receives this byte it also shifts it into the CRC-
generator and the result is a 16-bit CRC of the new data byte and the new address. With the next sixteen
read time slots the bus master will read this 16-bit CRC from the DS2450 to verify that the address
incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse
should be issued in order to repeat the Write Memory command sequence.
Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is
the result of shifting the command byte into the CRC-generator, followed by the two address bytes, and
finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2450
automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not
shifting) the new (incremented) address into the CRC-generator and then shifting in the new data byte.
The decision to continue after having received a bad CRC or if the verification fails is made entirely by
the bus master. Write access to the conversion read-out registers is not possible. If a write attempt is
made to a page 0 address the device will follow the Write Memory flow chart correctly but the
verification of the data byte read back from memory will usually fail. The Write Memory command
sequence can be ended at any point by issuing a Reset Pulse.