参数资料
| 型号： | DS2502G+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC OTP 1KBIT 2SFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EPROMs |
| 存储器类型： | EPROM OTP |
| 存储容量： | 1K（1K x 1） |
| 接口： | 1 线 串行 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 2-SFN |
| 供应商设备封装： | 2-SFN（6x6） |
| 包装： | 带卷 (TR) |
DS2502
Skip ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process
is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Application Note
187 for a comprehensive discussion of a ROM search, including an actual example.
1-Wire Signaling
The DS2502 requires strict protocols to ensure data integrity. The protocol consists of five types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data
and Program Pulse. All these signals except presence pulse are initiated by the bus master. The
initialization sequence required to begin any communication with the DS2502 is shown in Figure 10. A
Reset Pulse followed by a Presence Pulse indicates the DS2502 is ready to accept a ROM command. The
bus master transmits (TX) a reset pulse (t RSTL , minimum 480 μs). The bus master then releases the line
and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After
detecting the rising edge on the data pin, the DS2502 waits (t PDH , 15-60 μs) and then transmits the
presence pulse (t PDL , 60-240 μs).
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2502 to the master
by triggering a delay circuit in the DS2502. During write time slots, the delay circuit determines when the
DS2502 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2502 will hold the data line low overriding the “1” generated by the master.
If the data bit is a 1, the device will leave the read data time slot unchanged.
PROGRAM PULSE
To copy data from the 8-bit scratchpad to the 1024-bit EPROM Memory or Status Memory, a program
pulse of 12 volts is applied to the data line after the bus master has confirmed that the CRC for the current
byte is correct. During programming, the bus master controls the transition from a state where the data
line is idling high via the pullup resistor to a state where the data line is actively driven to a programming
voltage of 12 volts providing a minimum of 10 mA of current to the DS2502. This programming voltage
(Figure 12) should be applied for 480 μs, after which the bus master returns the data line to an idle high
state controlled by the pullup resistor. Note that due to the high-voltage programming requirements for
any 1-Wire EPROM device, it is not possible to multidrop non-EPROM based 1-Wire devices with the
DS2502 during programming. An internal diode within the non-EPROM based 1-Wire devices will
attempt to clamp the data line at approximately 8 volts and could potentially damage these devices.
相关PDF资料 |
PDF描述 |
|---|---|
| DS2502P+T&R | IC OTP 1KBIT 6TSOC |
| DS2502+T&R | IC OTP 1KBIT TO92-3 |
| 345-026-541-202 | CARDEDGE 26POS DUAL .100 GREEN |
| AYF534765 | CONN SOCKET FPC 0.5MM 47POS SMD |
| AYF534665 | CONN SOCKET FPC 0.5MM 46POS SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2502K | 功能描述:可擦除可编程ROM RoHS:否 制造商:Maxim Integrated 类型: 存储容量:1024 bit 组织:1 K x 1 接口类型: 工作电流:5 uA 编程电压: 工作电源电压:2.8 V to 6 V 最大工作温度:+ 85 C 安装风格:Through Hole 封装 / 箱体:TO-92 |
| DS2502P | 功能描述:可擦除可编程ROM RoHS:否 制造商:Maxim Integrated 类型: 存储容量:1024 bit 组织:1 K x 1 接口类型: 工作电流:5 uA 编程电压: 工作电源电压:2.8 V to 6 V 最大工作温度:+ 85 C 安装风格:Through Hole 封装 / 箱体:TO-92 |
| DS2-5-02P | 制造商:Cooper Bussmann 功能描述:TOP SCREW-ON INSERTION BRIDGE, 2 POLE, F - Bulk 制造商:COOPER BUSSMANN 功能描述:TOP SCREW-ON INSERTION BRIDGE, 2 POLE, F |
| DS2502P/R | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:1 kbit Add-Only Memory |
| DS2502P/T | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:1 kbit Add-Only Memory |
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