参数资料
型号: DS26324GN+
厂商: Maxim Integrated Products
文件页数: 31/120页
文件大小: 0K
描述: IC LIU 16CH T1/E1/J1 256CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
类型: 线路接口装置(LIU)
驱动器/接收器数: 16/16
规程: LIN
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 256-LBGA,CSBGA
供应商设备封装: 256-CSBGA(17x17)
包装: 托盘
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
18 of 120
Figure 5-3. Serial Port Operation for Read Access with CLKE = 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
A1
A2
A3
A4
A5
D1
D2
D3
D4
D5
D6
SCLK
SDI
SDO
CSB
(lsb)
(msb)
D0
(lsb)
D7
(msb)
A6
X
5.1.2
Parallel Port Operation
When using the parallel interface on the DS26324 the user has the option for either multiplexed bus operation or
nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26324 can
operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects
the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following Table lists all the
pins and their functions in the parallel port mode. See the timing diagrams in Section 9 for more details.
Table 5-1. Parallel Port Mode Selection and Pin Functions
MODESEL, MOTEL,
MUX
PARALLEL HOST
INTERFACE
ADDRESS, DATA, AND CONTROL
100
Nonmultiplexed Motorola
CSB, ACKB, DSB, RWB, ASB, A[5:0], D[7:0], INTB
110
Nonmultiplexed Intel
CSB, RDYB, WRB, RDB, ALE, A[5:0], D[7:0], INTB
101
Multiplexed Motorola
CSB, ACKB, DSB, RWB, ASB, AD[7:0], INTB
111
Multiplexed Intel
CSB, RDYB, WRB, RDB, ALE, AD[7:0], INTB
5.1.3
Interrupt Handling
There are four sets of events that can potentially trigger an Interrupt. The interrupt functions as follows:
When status changes on an interruptible event, INTB pin will go low if the event is enabled through the
corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10k
resister for
wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when
not active by setting register GISC.INTM.
When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source
of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The
Interrupt Status register can also be configured as clear on write as per register GISC.CWE. When set to clear
on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a ‘1’ to
it’s bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a
register without clearing them on all bits.
Subsequently the host processor can read the corresponding Status Register to check the real-time status of
the event.
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DS26324GN+T&R 功能描述:电信集成电路 3.3V E1/T1/J1 16Ch Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 类型:Telecom IC - Various 工作电源电压:4.75 V to 5.25 V 电源电流: 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-100 封装:Tray
DS26324GNA2 功能描述:电信集成电路 RoHS:否 制造商:STMicroelectronics 类型:Telecom IC - Various 工作电源电压:4.75 V to 5.25 V 电源电流: 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-100 封装:Tray
DS26324GNA2+ 功能描述:电信集成电路 RoHS:否 制造商:STMicroelectronics 类型:Telecom IC - Various 工作电源电压:4.75 V to 5.25 V 电源电流: 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-100 封装:Tray