DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
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LIST OF FIGURES
Figure 3-1. Block Diagram........................................................................................................................................... 8
Figure 3-2. Receive Logic Detail.................................................................................................................................. 9
Figure 3-3. Transmit Logic Detail................................................................................................................................. 9
Figure 5-1. Serial Port Operation for Write Access ................................................................................................... 18
Figure 5-2. Serial Port Operation for Read Access with CLKE = 0........................................................................... 18
Figure 5-3. Serial Port Operation for Read Access with CLKE = 1........................................................................... 19
Figure 5-4. Interrupt Handling Flow Diagram ............................................................................................................ 20
Figure 5-5. Pre-Scaler PLL and Clock Generator...................................................................................................... 21
Figure 5-6. T1 Transmit Pulse Templates ................................................................................................................. 24
Figure 5-7. E1 Transmit Pulse Templates................................................................................................................. 25
Figure 5-8. LIU Front End.......................................................................................................................................... 26
Figure 5-9. Jitter Attenuation ..................................................................................................................................... 32
Figure 5-10. Analog Loopback................................................................................................................................... 33
Figure 5-11 Digital Loopback..................................................................................................................................... 33
Figure 5-12. Remote Loopback................................................................................................................................. 34
Figure 5-13. PRBS Synchronization State Diagram.................................................................................................. 36
Figure 5-14. Repetitive Pattern Synchronization State Diagram............................................................................... 37
Figure 7-1. JTAG Functional Block Diagram............................................................................................................. 88
Figure 7-2. TAP Controller State Diagram................................................................................................................. 91
Figure 9-1. Intel Nonmuxed Read Cycle ................................................................................................................... 97
Figure 9-2. Intel Mux Read Cycle.............................................................................................................................. 98
Figure 9-3. Intel Nonmux Write Cycle...................................................................................................................... 100
Figure 9-4. Intel Mux Write Cycle ............................................................................................................................ 101
Figure 9-5. Motorola Nonmux Read Cycle .............................................................................................................. 103
Figure 9-6. Motorola Mux Read Cycle..................................................................................................................... 104
Figure 9-7. Motorola Nonmux Write Cycle .............................................................................................................. 106
Figure 9-8. Motorola Mux Write Cycle..................................................................................................................... 107
Figure 9-9. Serial Bus Timing Write Operation........................................................................................................ 108
Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 108
Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 108
Figure 9-12. Transmitter Systems Timing................................................................................................................ 109
Figure 9-13. Receiver Systems Timing ................................................................................................................... 110
Figure 9-14. JTAG Timing ....................................................................................................................................... 111
Figure 10-1. 256-Ball TEBGA.................................................................................................................................. 112