
DS26401 Octal T1/E1/J1 Framer
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8.20.3 HDLC Status and Information
RRTS5 and RLS5 provide status information for the receive HDLC controller. When a particular event has occurred
(or is occurring), the appropriate bit in one of these registers is set to 1. With the latched bits, when an event occurs
and a bit is set to 1, it remains set until the user reads that bit. The bit is cleared when it is read and it is not set
again until the event has occurred again. The real-time bits report the current instantaneous conditions that are
occurring and the history of these bits is not latched.
Like the other latched-status registers, the user follows a read of the status bit with a write. The byte written to the
register informs the device which of the latched bits the user wishes to clear (the real-time bits are not affected by
writing to the status register). The user writes a byte to one of these registers, with a 1 in the bit positions the user
wishes to clear and a zero in the bit positions the user wishes not to clear.
The HDLC status register RLS5 can initiate a hardware interrupt through the INT output signal. Each of the events
in this register can be either masked or unmasked from the interrupt pin through the receive-HDLC interrupt-mask
register (RIM5). Interrupts force the INT signal low when the event occurs. The INT pin is allowed to return high (if
no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
Register Name:
RRTS5
Register Description:
Receive Real-Time Status Register 5 (HDLC)
Register Address:
0B4h + (200h x n) : where n = 0 to 7, for Ports 1 to 8
Bit #
7
6
5
4
3
2
1
0
Name
—
PS2
PS1
PS0
—
RHWM
RNE
Default
0
Note: All bits in this register are real-time.
Bit 0 / Receive-FIFO Not Empty Condition (RNE).
Set when the receive 64-byte FIFO has at least one byte
available for a read. This is a real-time bit.
Bit 1 / Receive-FIFO Above High-Watermark Condition (RHWM).
Set when the receive 64-byte FIFO fills beyond
the high watermark as defined by the receive-HDLC FIFO control register (RHFC).This is a real-time bit.
Bits 2, 3, 7 / Unused
Bits 4 to 6 / Receive Packet Status (PS0 to PS2)
. These are real-time bits indicating the status as of the last read
of the receive FIFO.
PS2
PS1
PS0
PACKET STATUS
0
In Progress: End of message has not yet been reached.
0
1
Packet OK: Packet ended with correct CRC codeword.
0
1
0
CRC Error: A closing flag was detected, preceded by a corrupt CRC
codeword.
0
1
Abort: Packet ended because an abort signal was detected (seven or more
ones in a row).
1
0
Overrun: HDLC controller terminated reception of packet because receive
FIFO is full.