参数资料
型号: DS26503
英文描述: T1/E1/J1 BITS Element
中文描述: T1/E1/J1 BITS单元
文件页数: 59/123页
文件大小: 995K
代理商: DS26503
DS26503 T1/E1/J1 BITS Element
59 of 123
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0/Receive BOC Detector Change-of-State Event (RBOC).
Set whenever the BOC detector sees a change of state to a
valid BOC. The setting of this bit prompts the user to read the RFDL register.
Bit 1/Receive FDL Match Event (RMTCH).
Set whenever the contents of the RFDL register matches RFDLM1 or
RFDLM2.
Bit 2/TFDL Register Empty Event (TFDLE).
Set when the transmit FDL buffer (TFDL) empties.
Bit 3/RFDL Register Full Event (RFDLF).
Set when the receive FDL buffer (RFDL) fills to capacity.
Bit 4/RFDL Abort Detect Event (RFDLAD).
Set when eight consecutive ones are received on the FDL.
Bit 5/BOC Clear Event (BOCC).
Set when 30 FDL bits occur without an abort sequence.
Bit 6/Loss Of Transmit Clock Event (LOTC).
Set when the signal at the TCLK pin has not transitioned for approximately
15 periods of the scaled MCLK.
Bit 7/Receive AIS-CI Event (RAIS-CI)
(T1 Only).
Set when the receiver detects the AIS-CI pattern as defined in ANSI
T1.403.
SR3
Status Register 3
18h
7
6
5
4
3
2
1
0
RAIS-CI
0
LOTC
0
BOCC
0
RFDLAD
0
RFDLF
0
TFDLE
0
RMTCH
0
RBOC
0
X
X
X
X
X
X
X
X
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