参数资料
型号: DS26503L+
厂商: Maxim Integrated Products
文件页数: 65/122页
文件大小: 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: BITS 元件,多路复用器
PLL:
主要目的: T1/E1
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:2
差分 - 输入:输出: 无/无
频率 - 最大: 6.312MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
产品目录页面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
47 of 122
Table 9-1. E1 Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N and
N + 2, and FAS not present in
frame N + 1
Three consecutive incorrect FAS
received
Alternate: (E1RCR.2 = 1) The above
criteria is met or three consecutive
incorrect bit 2 of non-FAS received
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment
words found within 8ms
915 or more CRC4 code words out of
1000 received in error
G.706
4.2 and 4.3.2
CAS
Valid MF alignment word
found and previous time slot
16 contains code other than
all zeros
Two consecutive MF alignment
words received in error
G.732 5.2
Register Name:
E1TCR
Register Description:
E1 Transmit Control Register
Register Address:
1Eh
Bit #
7
6
5
4
3
2
1
0
Name
TFPT
TSiS
THDB3
Default
0
HW
Mode
0
HBE
PIN 55
0
Bits 0, 2, 3, 5, 6: Unused, must be set = 0 for proper operation.
Bit 1: Transmit HDB3 Enable (THDB3)
0 = HDB3 disabled
1 = HDB3 enabled
Bit 4: Transmit International Bit Select (TSiS)
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to 0)
Bit 7: Transmit Time Slot 0 Pass-Through (TFPT)
0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
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