
DS26518 8-Port T1/E1/J1 Transceiver
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9.13 Bit Error-Rate Test Function (BERT)
The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating bit patterns. It
is used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers.
The registers related to the configure, control, and status of the BERT are shown in
Table 9-45.Table 9-45. Registers Related to Configure, Control, and Status of BERT
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Global BERT Interrupt Status Register 1
00FAh
When any of the 8 BERTs issue an interrupt, a
bit is set.
Global BERT Interrupt Mask Register 1
00FDh
When any of the 8 BERTs issue an interrupt, a
bit is set.
Receive Expansion Port Control Register
08Ah
Enable for the receiver BERT.
Receive BERT Port Bit Suppress Register
08Bh
Bit suppression for the receive BERT.
Receive BERT Port Channel Select
0D4h, 0D5h,
0D6h, 0D7h
Channels to be enabled for the framer to accept
data from the BERT pattern generator.
Transmit Expansion Port Control Register
18Ah
Enable for the transmitter BERT.
Transmit BERT Port Bit Suppress Register
18Bh
Bit suppression for the transmit BERT.
Transmit BERT Port Channel Select
1D4h, 1D5h,
1D6h, 1D7h
Channels to be enabled for the framer to accept
data from the transmit BERT pattern generator.
BERT Alternating Word Count Rate Register
1100h
BERT alternating pattern count register.
BERT Repetitive Pattern Set Register 1
1101h
BERT repetitive pattern set register 1.
BERT Repetitive Pattern Set Register 2
1102h
BERT repetitive pattern set register 2.
BERT Repetitive Pattern Set Register 3
1103h
BERT repetitive pattern set register 3.
BERT Repetitive Pattern Set Register 4
1104h
BERT repetitive pattern set register 4.
BERT Control Register 1
(BC1)
1105h
Pattern selection and misc control.
BERT Control Register 2
(BC2)
1106h
BERT bit pattern length control.
BERT Bit Count Register 1
(BBC1)
1107h
Increments for BERT bit clocks.
BERT Bit Count Register 2
(BBC2)
1108h
BERT bit counter.
BERT Bit Count Register 3
(BBC3)
1109h
BERT bit counter.
BERT Bit Count Register 4
(BBC4)
110Ah
BERT bit counter.
BERT Error Count Register 1
(BEC1)
110Bh
BERT error counter.
BERT Error Count Register 2
(BEC2)
110Ch
BERT error counter.
BERT Error Count Register 3
(BEC3)
110Dh
BERT error counter.
BERT Status Register (
BSR)
110Eh
Denotes synchronization loss and other status.
BERT Status Interrupt Mask Register (
BSIM)
110Fh
BERT interrupt mask.
BERT Control Register 3
(BC3)
1400h
Pattern selection and misc control.
BERT Real-Time Status Register
(BRSR)1401h
Denotes synchronization loss and other status.
BERT Latched Status Register 1 (
BLSR1)
1402h
Denotes synchronization loss and other status.
BERT Status Interrupt Mask Register 1
1403h
BERT interrupt mask.
BERT Latched Status Register 2 (
BLSR2)
1404h
BERT error status.
BERT Status Interrupt Mask Register 2
1405h
BERT interrupt mask.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer N = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 8 for Framers 2 to 8.