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参数资料
| 型号： | DS2720CU/T&R |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封装： | MICRO, SOP-8 |
| 文件页数： | 4/21页 |
| 文件大小： | 264K |
| 代理商： | DS2720CU/T&R |
DS2720
12 of 21
Figure 8. 1-WIRE NET ADDRESS FORMAT
8-Bit CRC
48-Bit Serial Number
8-Bit Family
Code (31h)
MSb
LSb
CRC GENERATION
The DS2720 has an 8-bit cyclic redundancy check (CRC) stored in the most significant byte of its 1-Wire
net address. To ensure error-free transmission of the address, the host system can compute a CRC value
from the first 56 bits of the address and compare it to the CRC from the DS2720. The host system is
responsible for verifying the CRC value and taking action as a result. The DS2720 does not compare
CRC values and does not prevent a command sequence from proceeding as a result of a CRC mismatch.
Proper use of the CRC can result in a communication channel with a very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as
shown in Figure 9, or it can be generated in software. Additional information about the Dallas 1-Wire
CRC is available in Application Note 27, Understanding and Using Cyclic Redundancy Checks with
Dallas Semiconductor Touch Memory Products
.
In the circuit in Figure 9, the shift register bits are initialized to 0. Then, starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value.
Figure 9. 1-WIRE CRC GENERATION BLOCK DIAGRAM
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2720 uses an open-drain output driver as part of the
bidirectional interface circuitry shown in Figure 10. If a bidirectional pin is not available on the bus
master, separate output and input pins can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5k
W. The idle state for the 1-Wire bus is high. If, for any
reason, a bus transaction must be suspended, the bus must be left in the idle state in order to properly
resume the transaction later. If the bus is left low for more than 120ms, slave devices on the bus begin to
interpret the low period as a reset pulse, effectively terminating the transaction.
MSb
XOR
LSb
XOR
INPUT
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