参数资料
型号: DS2741N+T
厂商: Maxim Integrated Products
文件页数: 7/10页
文件大小: 0K
描述: IC MONITOR/ACCUMULATOR 14-TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 燃料,电量检测计/监控器
电池化学: 锂离子(Li-Ion)
电源电压: 2.5 V ~ 4.5 V
工作温度: -20°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 14-WFDFN 裸露焊盘
供应商设备封装: 14-TDFN-EP(3x3)
包装: 带卷 (TR)
Current Monitor and Accumulator with
Integrated Sense Resistor
Registers
The DS2741 has 2-byte registers for current measure-
ment and accumulation. When the MSB of a 2-byte reg-
ister is read, both the MSB and LSB are latched and
held for the duration of the read data command to pre-
vent updates during the read and ensure synchroniza-
tion between the two register bytes. For consistent
results, always read the MSB and the LSB of a 2-byte
register during the same read data command sequence.
Table 1. Register Map
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is idle
it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low, while SCL
remains high, generates a START condition. See
Figure 4 for applicable timing.
ADDRESS
(HEX)
00h to 0Fh
DESCRIPTION
Reserved
READ/WRITE
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high, while SCL
10h and 11h Current Accumulator Register
12h and 13h Reserved
14h Temperature Register
R/ W
R
remains high, generates a STOP condition. See
Figure 4 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
15h
Reserved
transfer to indicate that it will immediately initiate a
16h and 17h Current Register
R
new data transfer following the current one.
18h to FFh
Reserved
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
I 2 C Bus Interface
I 2 C Definitions
The following terminology is commonly used to
describe I 2 C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
SDA
t BUF
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 4 for applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse of
SCL plus the setup and hold-time requirements (see
Figure 4). Data is shifted into the device during the
rising edge of the SCL.
t LOW
t F
t HD:STA
t SP
SCL
t HD:STA
t R
t HIGH
t SU:STA
t SU:STO
t HD:DAT
t SU:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V IL(MAX) AND V IH(MIN) .
Figure 4. I 2 C Timing Diagram
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