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参数资料
| 型号： | DS2782G+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | IC FUEL GAUGE BATT 10-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 锂离子（Li-Ion）、锂聚合物（Li-Pol） |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 供应商设备封装： | 10-TDFN-EP（3x4） |
| 包装： | 带卷 (TR) |
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DS2782
Table 3. Parameter EEPROM Memory Block 1
ADDRESS
(HEX)
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
DESCRIPTION
CONTROL - Control Register
AB - Accumulation Bias
AC - Aging Capacity MSB
AC - Aging Capacity LSB
VCHG - Charge Voltage
IMIN - Minimum Charge Current
VAE - Active Empty Voltage
IAE - Active Empty Current
Active Empty 40
RSNSP - Sense Resistor Prime
Full 40 MSB
Full 40 LSB
Full 3040 Slope
Full 2030 Slope
Full 1020 Slope
Full 0010 Slope
ADDRESS
(HEX)
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
DESCRIPTION
AE 3040 Slope
AE 2030 Slope
AE 1020 Slope
AE 0010 Slope
SE 3040 Slope
SE 2030 Slope
SE 1020 Slope
SE 0010 Slope
RSGAIN - Sense Resistor Gain MSB
RSGAIN - Sense Resistor Gain LSB
RSTC - Sense Resistor Temp. Coeff.
FRSGAIN - Factory Gain MSB
FRSGAIN - Factory Gain LSB
Reserved
2-Wire Slave Address
Reserved
2-WIRE BUS SYSTEM
The 2-Wire bus system supports operation as a slave only device in a single or multi-slave, and single or multi-
master system. Up to 128 slave devices may share the bus by uniquely setting the 7-bit slave address. The 2-wire
interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional
communication between the DS2782 slave device and a master device at speeds up to 400 kHz. The DS2782’s
SDA pin operates bi-directionally, that is, when the DS2782 receives data, SDA operates as an input, and when the
DS2782 returns data, SDA operates as an open drain output, with the host system providing a resistive pull-up.
The DS2782 always operates as a slave device, receiving and transmitting data under the control of a master
device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and
STOP bits which begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and
then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any
change in SDA when SCL is high is interpreted as a START or STOP control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high
when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL
is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one
transaction and begin another without returning the bus to the idle state. In multi-master systems, a Repeated
START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities
in which the SDA transitions when SCL is high.
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| DS2782K | 功能描述:电源管理IC开发工具 RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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