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参数资料
| 型号： | DS28EC20+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/27页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 20KBIT TO92-3 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 20K（256 x 80） |
| 接口： | 1 线 串行 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | TO-226-3、TO-92-3（TO-226AA）成形引线 |
| 供应商设备封装： | TO-92-3 |
| 包装： | 带卷 (TR) |
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DS28EC20: 20Kb 1-Wire EEPROM
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System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Typical value represents the internal parasite capacitance when V PUP is first applied. Once the parasite capacitance is charged, it
does not affect normal communication.
Guaranteed by design, characterization and/or simulation only. Not production tested.
V TL , V TH , and V HY are a function of the internal supply voltage which is itself a function of V PUP , R PUP , 1-Wire timing, and
capacitive loading on I/O. Lower V PUP , higher R PUP , shorter t REC , and heavier capacitive loading all lead to lower values of V TL , V TH ,
and V HY .
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to V ILMAX at all times the master is driving I/O to a logic 0 level.
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After V TH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least V HY to be detected as logic 0.
The I-V characteristic is approximately linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t REH after V TH has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to 1/(t W0LMIN + t RECMIN ).
Interval after t RSTL during which a bus master can read a logic 0 on I/O if there is a DS28EC20 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V IL to V TH . The actual
maximum duration for the master to pull the line low is t W1LMAX + t F - ε and t W0LMAX + t F - ε , respectively.
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V IL to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is t RLMAX + t F .
Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval
should be such that the voltage at I/O is greater than or equal to 3.0V. For 3.3V±5% V PUP operation of the DS28EC20, a low-
impedance bypass of R PUP , which can be activated during programming, is required.
The t PROG interval begins t REHMAX after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I PROG to I L .
Write-cycle endurance is degraded as T A increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T A increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
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