参数资料
型号: DS3150Q
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQCC28
封装: PLASTIC, LCC-28
文件页数: 3/22页
文件大小: 228K
代理商: DS3150Q
DS3150
11 of 22
SECTION 2: SIGNAL DESCRIPTIONS
Table 2A below lists all of the signals on the DS3150 and their function. The signals are listed in
alphabetical order. Section 4 shows the signal pin assignments for each package option.
SIGNAL DESCRIPTIONS Table 2A
Signal
Name
I/O
Description
DM*
O
Driver Monitor (active low, open drain). This signal reports the status of the transmit
driver monitor. When the transmit driver monitor detects a faulty transmitter, this
pin is pulled low. This pin should have an external pull-up to VDD. This signal is not
bonded out in the PLCC package.
EFE
I3
Enhanced Feature Enable. This signal enables the enhanced DS3150 features (PRBS
generation/detection; transmit driver monitor; and transmission of patterns, including
all ones, T3 AIS or the 1010… pattern).
0 = Enhanced Features Disabled: TDS0 and TDS1 ignored, and PRBS tri-stated
1 = Enhanced Features Enabled: TDS0, TDS1, and PRBS active
Float = Test Mode Enabled: TDS0, TDS1, LBO, LOS* redefined as test pins
ICE
I3
Invert Clock Enable. This signal determines on which RCLK edge RPOS/RNRZ and
RNEG/RLCV are updated and on which TCLK edge TPOS/TNRZ and TNEG are
sampled.
0 = Normal RCLK / Normal TCLK: update RPOS/RNRZ and RNEG/RLCV on
falling edge of RCLK; sample TPOS/TNRZ and TNEG on rising edge of TCLK
1 = Normal RCLK / Inverted TCLK: update RPOS/RNRZ and RNEG/RLCV on
falling edge of RCLK; sample TPOS/TNRZ and TNEG on falling edge of TCLK
Float = Inverted RCLK / Inverted TCLK: update RPOS/RNRZ and RNEG/RLCV on
rising edge of RCLK; sample TPOS/TNRZ and TNEG on falling edge of TCLK
LBKS*
I3
Loopback Select. This input determines if either the Analog Loopback or the
Remote Loopback is enabled. See the Block Diagram in Section 1 for details.
0 = Analog Loopback Enabled
1 = No Loopback Enabled
Float = Remote Loopback Enabled
LBO
I
Line Build-Out. This input indicates cable length for waveform shaping in DS3 and
STS-1 modes. LBO is ignored for E3 mode.
0 = Cable length greater than or equal to 225 feet.
1 = Cable length less than 225 feet.
LOS*
O
Loss Of Signal (active low). This signal will be asserted upon detection of 192
±1
consecutive zeros. Signals lower than 21dB below nominal are squelched. LOS* is
deasserted when there are no Excessive Zero occurrences over a span of 192
±1 clock
periods. An Excessive Zero occurrence is defined as 3 or more consecutive zeros in
the T3 and STS-1 modes or 4 or more zeros in the E3 mode.
Governing
Specifications are ANSI T1.231 and ITU G.775.
MCLK
I
Master Clock. The clock input at this signal is used by the clock and data recovery
machine. A T3 (44.736 MHz
± 20 ppm), E3 (34.368 MHz ± 20 ppm), or STS-1
(51.840 MHz
± 20 ppm) clock should be applied at this signal. Tying this pin high or
leaving it floating forces the device to use the clock applied at the TCLK input for the
receive side clock and data recovery.
Tying this pin low enables an internal
oscillator. The frequency of this oscillator is determined by a resistor placed between
OFSEL and VSS. MCLK has an internal 15 k pull-up resistor to VDD.
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DS3150QC1+ 功能描述:网络控制器与处理器 IC 3.3V DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS3150QN 功能描述:网络控制器与处理器 IC 3.3V DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray