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| 型号： | DS3174N+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/234页 |
| 文件大小： | 0K |
| 描述： | IC QUAD DS3/E3 TXRX 400-PBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 功能： | 单芯片收发器 |
| 接口： | DS3，E3 |
| 电路数： | 4 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 725mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-BBGA |
| 供应商设备封装： | 400-PBGA（27x27） |
| 包装： | 托盘 |
| 包括： | DS3 调帧器，E3 调帧器，HDLC 控制器，芯片内 BERT |
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DS3171/DS3172/DS3173/DS3174
103
stored in the highest numbered bit (5). This is to differentiate between a code in a register and the corresponding
code in a signal.
10.9.3.1 Transmit Data Storage
The Transmit Data Storage block contains the registers for two FEAC codes (C{1:6]) and controller circuitry for
reading and writing the memory. The Transmit Data Storage receives data from the microprocessor interface, and
stores the data in memory. The Transmit FEAC Processor reads the data from the Transmit Data Storage.
10.9.3.2 Transmit FEAC Processor
The Transmit FEAC Processor accepts data from the Transmit Data Storage performs FEAC processing. The
FEAC codes are read from Transmit Data Storage with the MSB (C[1]) in TFCA[0] or TFCB[0], and the LSB (C[6])
in TFCA[5] or TFCB[5].
FEAC processing has four modes of operation (Idle, single code, dual code, and continuous code). In Idle mode, all
ones are output on the outgoing FEAC data stream. In single code mode, the code from TFCA[5:0] is inserted into
a codeword (See Figure 10-24), and sent ten consecutive times. Once the ten codewords have been sent, all ones
are output. In dual code mode, the code from TFCA[5:0] is inserted into a codeword, and sent ten consecutive
times. Then the code from TFCB[5:0] is inserted into a codeword, and sent ten consecutive times. Once both
codewords have both been sent ten times, all ones are output. In continuous mode, the code from TFCA[5:0] is
inserted into a codeword, and sent until the mode is changed
10.9.3.3 Receive FEAC Processor
The Receive FEAC Processor accepts an incoming data line and extracts all overhead and performs FEAC code
extraction , and Idle detection.
Figure 10-24. FEAC Codeword Format
Cx - FEAC Code
Receive/Transmit Order
1
0
C6
0
MSB
1
LSB
16
1
C5 C4 C3 C2 C1
FEAC code extraction determines the codeword boundary by identifying the codeword sequence and extracts the
FEAC code. A FEAC codeword is a repeating 16-bit pattern (See Figure 10-24). The codeword sequence is the
pattern (0xxxxxx011111111) that contains each FEAC code (C[6:1]). Each time slot is checked for a codeword
sequence. Once a codeword sequence is found, the FEAC code is checked. If the same FEAC code is received in
three consecutive codewords without errors, the FEAC code detection indication is set, and the FEAC code is
stored in the Receive FIFO with the MSB (C[1]) in RFF[0], and the LSB (C[6]) in RFF[5]. The FEAC code detection
indication is cleared if two consecutively received FEAC codewords differ from the current FEAC codeword, or a
FEAC Idle condition is detected.
Idle detection detects a FEAC Idle condition. A FEAC idle condition is declared if sixteen consecutive ones are
received. The FEAC Idle condition is terminated when the FEAC code detection indication is set.
10.9.3.4 Receive FEAC FIFO
The Receive FIFO block contains memory for four FEAC codes (C[1:6]) and controller circuitry for reading and
writing the memory. The Receive FIFO controller functions include filling the memory, tracking the memory fill level,
maintaining the memory read and write pointers, and detecting memory overflow and underflow conditions. The
Receive FIFO accepts data from the Receive FEAC Processor and stores the data in memory. The data is read
from the receive FIFO via the microprocessor interface. The Receive FIFO also outputs FIFO fill status (empty) via
the microprocessor interface. All operations are code based (six bits). The Receive FIFO is considered empty when
it does not contain any data. The Receive FIFO accepts data from the Receive FEAC Processor until full. If a
FEAC code is received while full, the data is discarded and a FIFO overflow condition is declared. If the Receive
FIFO is read while the FIFO is empty, the read is ignored.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3174N+ | 功能描述:网络控制器与处理器 IC Quad DS3/E3 Single Chip Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3177+ | 制造商:Maxim Integrated Products 功能描述:IC TXRX DS3/E3 CSBGA |
| DS3177N+ | 制造商:Maxim Integrated Products 功能描述:DS3/E3 SINGLE-CHIP TRANSCEIVER - Rail/Tube 制造商:Maxim Integrated Products 功能描述:IC TXRX DS3/E3 CSBGA |
| DS3177N+T | 制造商:Maxim Integrated Products 功能描述:DS3/E3 SINGLE-CHIP TRANSCEIVER - Tape and Reel |
| DS-318 | 制造商:MA-COM 制造商全称:M/A-COM Technology Solutions, Inc. 功能描述:Plug-In Two-Way Power Divider, 5 - 500 MHz |
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