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| 型号： | DS3174N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/234页 |
| 文件大小： | 0K |
| 描述： | IC QUAD DS3/E3 TXRX 400-PBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 功能： | 单芯片收发器 |
| 接口： | DS3，E3 |
| 电路数： | 4 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 725mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-BBGA |
| 供应商设备封装： | 400-PBGA（27x27） |
| 包装： | 托盘 |
| 包括： | DS3 调帧器，E3 调帧器，HDLC 控制器，芯片内 BERT |
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DS3171/DS3172/DS3173/DS3174
100
Programmable trace ID multi-frame alignment – The transmit side can be programmed to perform trail trace
multi-frame alignment insertion. The receive side can be programmed to perform trail trace multi-frame
synchronization.
Programmable bit reordering – The trace identifier data can be output MSB first or LSB first from the data
storage.
Programmable data inversion – The trace identifier data can be inverted immediately after trace ID
processing on the transmit side, and immediately before trail ID processing on the receive side.
Fully independent transmit and receive sides
Fully independent Line side and register interface timing – The data storage can be read from or written to
via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to
via the line side while all microprocessor interface clocks and signals are inactive.
10.8.3 Functional Description
The bits in a byte are received most significant bit (MSB) first and least significant bit (LSB) last. When they are
output serially, they are output MSB first and LSB last. The bits in a byte in an incoming signal are numbered in the
order they are received, 1 (MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the
highest numbered bit (7), and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a
byte in a register and the corresponding byte in a signal.
10.8.4 Transmit Data Storage
The Transmit Data Storage block contains memory for 16 bytes of data and controller circuitry for reading and
writing the memory. The Transmit Data Storage controller functions include filling the memory and maintaining the
memory read and write pointers. The Transmit Data Storage receives data from the microprocessor interface, and
stores the data in memory. The Transmit Trace ID Processor reads the data from the Transmit Data Storage. The
Transmit Data Storage contains the transmit trail trace identifier. Note: The contents of the transmit trail (path) trace
identifier memory will be random data immediately after power-up, and will not change during a reset (
RST or DRST
low).
10.8.5 Transmit Trace ID Processor
The Transmit Trace ID Processor accepts data from Transmit Data Storage, processes the data according to the
Transmit Trace ID mode, and outputs the serial trace ID data stream.
10.8.6 Transmit Trail Trace Processing
The Transmit Trail Trace Processing accepts data from the Transmit Data Storage performs bit reordering and
multi-frame alignment insertion.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is input from the Transmit Data Storage with the MSB
in TTD[7] and the LSB in TTD[0] of the transmit trace ID data TTD[7:0]. If bit reordering is enabled, the outgoing 8-
bit data stream DT[1:8] is input from the Transmit Data Storage with the MSB is in TTD[0] and the LSB is in TTD[7]
of the transmit trace ID data TTD[7:0]. DT[1] is the first bit transmitted on the outgoing data stream.
Multi-frame alignment insertion overwrites the MSB of each trail trace byte with the multi-frame alignment signal.
The MSB of the first byte in the trail trace identifier is overwritten with a one, the MSB of the other fifteen bytes in
the trail trace identifier are overwritten with a zero. Multi-frame alignment insertion is programmable (on or off).
If transmit data inversion is enabled, the outgoing data is inverted after trail trace processing is performed. Transmit
data inversion is programmable (on or off). If transmit trail trace identifier idle (Idle) is enabled, the trail trace data is
overwritten with all zeros. Transmit Idle is programmable (on or off).
10.8.7 Receive Trace ID Processor
The Receive Trace ID Processor receives the incoming serial trace ID data stream and processes the incoming
data according to the Receive Trace ID mode, and passes the trace ID data on to Receive Data Storage.
The bits in a byte are received MSB first, LSB last. The bits in a byte in an incoming signal are numbered in the
order they are received, 1 (MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the
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