
DS3181/DS3182/DS3183/DS3184
220
Register Name:
GL.CR1
Register Description:
Global Control Register 1
Register Address:
002h
Bit #
15
14
13
12
11
10
9
8
Name
GWRM
INTM
DIREN
—
SIW1
SIW0
SIM1
SIM0
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
TMEI
MEIMS
GPM1
GPM0
PMU
LSBCRE
RSTDP
RST
Default
0
1
0
Bit 15: Global Write Mode (GWRM) This bit enables the global write mode. When this bit is set, a write to the
register of any port will write to the same register in all the ports. Reading the registers of any port is not supported
and will read back undefined data.
0 = Normal write mode
1 = Global write mode
Bit 14:
INT pin mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
0 = Pin is high impedance when not active
1 = Pin drives high when not active
Bit 13: Direct Status Enable (DIREN) This bit selects between the direct status and polled status modes for
UTOPIA and POS-PHY.
0 = Polled status mode
1 = Direct status mode
Bits 11 and 10: System Interface Bus Width (SIW[1:0]) These bits configure the system bus width.
00 = 8-bit
01 = 16-bit
1X = 32-bit
Bits 9 and 8: System Interface Mode (SIM[1:0]) These bits configure the system bus mode.
00 = UTOPIA L2
01 = UTOPIA L3
10 = POS-PHY L2
11 = POS-PHY L3 or SPI-3
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used insert an error in all ports and error insertion logic
configured for global error insertion. An error(s) is inserted at the next opportunity when this bit transitions from low
to high. The
GL.CR1.MEIMS bit must be clear for this bit to operate.
Bit 6: Transmit Manual Error Insert Select (MEIMS) This bit is used to select the source of the global manual
error insertion signal
0 = Global error insertion using TMEI bit
1 = Global error insertion using the GPIO6 pin
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]) These bits select the global performance
monitor register update mode.
00 = Global PM update using the PMU bit
01 = Global PM update using the GPIO8 pin
1x = One second PM update using the internal one second counter
Bit 3: Global Performance Monitor Update Register (PMU) This bit is used to update all of the performance
monitor registers configured to use this bit. When this bit is toggled from low to high the performance registers
configured to use this signal will be updated with the latest count value from the counters, and the counters will be
reset. The bit should remain high until the performance register update status bit (
GL.SR.PMS) goes high, then it
should be brought back low which clears the PMS status bit.