参数资料
型号: DS3232MZ+TRL
厂商: Maxim Integrated Products
文件页数: 9/23页
文件大小: 0K
描述: IC RTC W/SRAM I2C 8SOIC
标准包装: 2,500
类型: 时钟/日历
特点: 警报器,闰年,方波输出,SRAM
存储容量: 236B
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 2.3 V ~ 4.5 V
电压 - 电源,电池: 2.3 V ~ 4.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
DS3232M
±5ppm, I2C Real-Time Clock with SRAM
17
Maxim Integrated
Status Register (0Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
BB32KHZ
0
EN32KHZ
BSY
A2F
A1F
1
0
1
X
BIT 7
OSF: Oscillator stop flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for
some period and could be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time
that the oscillator stops. This bit remains at logic 1 until written to logic 0. The following are examples of
conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are insufficient to support the oscillator.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the oscillator (i.e., noise, leakage, etc.).
BIT 6
BB32KHZ: Battery-backed 32kHz output (BB32KHZ). This bit enables the 32kHz output when the device is pow-
ered from VBAT (provided the 32kHz output is enabled with the EN32KHZ bit). If BB32KHZ = 0, the 32kHz output
is forced low when the device is powered by VBAT.
BITS 5:4
Unused (0). These bits have no meaning and are fixed at 0 when read.
BIT 3
EN32KHZ: Enabled 32.768kHz output. This bit enables and disables the 32KHZ output. When set to a logic 0,
the 32KHZ output is high impedance. On initial power-up, this bit is set to a logic 1 and the 32KHZ output is
enabled and produces a 32.768kHz square wave if the oscillator is enabled.
BIT 2
BSY: Busy. This bit indicates the device is busy executing temperature conversion function. It goes to logic 1
when the conversion signal to the temperature sensor is asserted, and then it is cleared when the device has
completed the temperature conversion. See the Block Diagram for more details.
BIT 1
A2F: Alarm 2 flag. A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the
A2IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A2F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
BIT 0
A1F: Alarm 1 flag. A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the
A1IE bit is logic 1 and the INTCN bit is set to logic 1, INT/SQW is also asserted. A1F is cleared when written to
logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
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