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参数资料
| 型号： | DS3501U+T&R/C |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC POT NV 128POS HV 10-USOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 3,000 |
| 接片： | 128 |
| 电阻（欧姆）： | 10k |
| 电路数： | 1 |
| 温度系数： | 标准值 200 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（设备位址） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-µMAX |
| 包装： | 带卷 (TR) |
DS3501
High-Voltage, NV, I2C POT with Temp Sensor
and Lookup Table
4
_____________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TA = +70°C
50,000
EEPROM Write Cycles
TA = +25°C
200,000
Writes
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are nega-
tive.
Note 2: ICC is specified with the following conditions: SCL = 400kHz; SDA pulled up; and RL, RW, RH floating.
Note 3: ICC is specified with the following conditions: SCL, SDA pulled up; RL, RW, RH floating; and temperature sensor on.
Note 4: ISTBY is specified with SDA = SCL = VCC = 5.5V, resistor pins floating, and CR2 bit 0 = logic-high.
Note 5: This is the minimum VCC voltage that causes NV memory to be recalled.
Note 6: This is the time from VCC > VPOR until initial memory recall is complete.
Note 7: Guaranteed by design.
Note 8: Integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resis-
tor setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured
maximum setting. INL = [V(RW)i - (V(RW)0] / LSB(ideal) - i, for i = 0...127.
Note 9: Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The
expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
DNL = [V(RW)i+1 - (V(RW)i] / LSB(ideal) - 1, for i = 0...126.
Note 10: ZS error = code 0 wiper voltage divided by one LSB(ideal).
Note 11: FS error = (code 127 wiper voltage - V+) divided by one LSB (ideal).
Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard
mode timing.
Note 13: CB—total capacitance of one bus line in picofarads.
Note 14: EEPROM write time begins after a STOP condition occurs.
Note 15: Pulses narrower than max are suppressed.
I2C AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40°C to +100°C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 3.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Data Hold Time
tHD:DAT
0
0.9
s
Data Setup Time
tSU:DAT
100
ns
START Setup Time
tSU:STA
0.6
s
SDA and SCL Rise Time
tR
(Note 13)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 13)
20 +
0.1CB
300
ns
STOP Setup Time
tSU:STO
0.6
s
SDA and SCL Capacitive
Loading
CB
(Note 13)
400
pF
EEPROM Write Time
tW
(Note 14)
10
20
ms
Pulse-Width Suppression Time at
SDA and SCL Inputs
tIN
(Note 15)
50
ns
A0, A1 Setup Time
tSU:A
Before START
0.6
s
A0, A1 Hold Time
tHD:A
After STOP
0.6
s
SDA and SCL Input Buffer
Hysteresis
0.05 x
VCC
V
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