- 您现在的位置：买卖IC网 > PDF目录9189 > DS3501U+T&R (Maxim Integrated Products)IC POT NV 128POS HV 10-USOP PDF资料下载
参数资料
| 型号： | DS3501U+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/14页 |
| 文件大小： | 0K |
| 描述： | IC POT NV 128POS HV 10-USOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 3,000 |
| 接片： | 128 |
| 电阻（欧姆）： | 10k |
| 电路数： | 1 |
| 温度系数： | 标准值 200 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（设备位址） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-µMAX |
| 包装： | 带卷 (TR) |
DS3501
High-Voltage, NV, I2C POT with Temp Sensor
and Lookup Table
____________________________________________________________________
11
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition.
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses, including when it is reading bits from the
slave.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans-
mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
Byte read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
SDA
SCL
tHD:STA
tLOW
tHIGH
tR
tF
tBUF
tHD:DAT
tSU:DAT
REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
START
Figure 3. I2C Timing Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| DS3502U+T&R/C | IC POT DGTL NV 128TAP 10-USOP |
| DS3502U+T&R | IC POT DGTL NV 128TAP 10-MSOP |
| DS3501U+T&R/H | IC POT NV 128POS HV 10-USOP |
| DS3501U+T&R/C | IC POT NV 128POS HV 10-USOP |
| X9258UV24IZ-2.7 | IC XDCP QUAD 256TP 50K 24-TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3501Z+ | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| DS3501Z+T&R | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| DS3502 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:High-Voltage, NV, I2C POT |
| DS3502_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:High-Voltage, NV, I2C POT |
| DS35-02P | 制造商:Cooper Bussmann 功能描述:TOP SCREW-ON INSERTION BRIDGE, 2 POLE, F - Bulk 制造商:COOPER INDUSTRIES 功能描述:Top Screw-on insertion bridge, 2 pole, f 制造商:COOPER BUSSMANN 功能描述:TOP SCREW-ON INSERTION BRIDGE, 2 POLE, F |
发布紧急采购，3分钟左右您将得到回复。