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DS3803
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READ MODE
The DS3803 executes a read cycle whenever WE (Write enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A0 -
A14) defines which byte of data is to be accessed from the selected SRAMs. Valid data will be available
to the data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later occurring signal and the limiting parameter is
either tCO for CE or tOE for OE rather than tACC .
WRITE MODE
The DS3803 executes a write cycle whenever both WE and CE signals are in the active (low) state after
address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active),
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS3803 provides full functional capability for VCC greater than 4.5 volts and write-protects by 4.25
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAM constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically
write-protects itself, all inputs become don’t care, and all outputs become high impedance. As VCC falls
below approximately 3.0 volts, power switching circuits connect the lithium energy sources to the RAMs
to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching
circuits connect external VCC to the RAMs and disconnects the lithium energy source. Normal RAM
operation can resume after VCC exceeds 4.5 volts.
The DS3803 checks battery status to warn of potential data loss. Each time that VCC power is restored to
the DS3803, the battery voltages are checked with precision comparators. If both batteries providing
backup power to a particular SRAM are less than 2.0 volts, the second memory access to that SRAM is
inhibited. Battery status for each SRAM can therefore be determined by a three-step process. First, a read
cycle is performed to any location within that SRAM in order to save the contents of that location. A
subsequent write cycle can then be executed to the same memory location, altering data. If a subsequent
read cycle fails to verify the written data, then battery voltage for that SRAM is less than 2.0V and data is
in danger of being lost.
The DS3803 also provides battery redundancy. In many applications data integrity is paramount. The
DS3803 provides two batteries for each SRAM and an internal isolation switch to select between them.
During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the
other automatically takes over. The switch between batteries is transparent to the user.